Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-12-08
2002-09-24
Gaffin, Jeffrey (Department: 2182)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S032000, C710S057000, C712S227000
Reexamination Certificate
active
06457144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention pertains to capturing trace data. More particularly, it pertains to capturing trace data for storage in main store.
2. Background Art
Processor architectures often provide mechanisms for capturing instruction streams to aid performance analysis. However, there is also a need to provide for capture of processor bus and I/O bus behavior which is useful for analyzing memory controller performance. Further, having detailed and accurate information about instruction frequency and sequences is important for developing designs having high performance.
On-chip entities known as trace arrays which are used to collect information useful for debug have finite depth and are often not deep enough to capture enough information to completely analyze a problem. A solution which has been used to address this problem provides off-chip signals (chip I/Os) to convey this same information to an external logic analyzer. This solution is costly since it reserves chip I/Os for problem debug which otherwise could be used to enhance performance or function.
U.S. Pat. No. 5,355,487 describes a software tracing system in which a trace buffer is configured as two buffers. This system requires the use of a trace hook and timer interrupts for controlling the interrupt mechanism. There is a need in the art for a method and system for tracing many facilities each hardware cycle and is, therefore, not constrained by a timer interrupt mechanism.
Other software tracing systems provide for storing memory references into a software trace buffer when code inserted into an instruction stream by a linker specifies that a storage reference should be stored to the trace buffer. Such systems require link code modification to insert trace buffer update instructions into the instruction stream, resulting in an undesirable change in the characteristics of the mechanism being tested.
It is an object of the invention to provide an improved trace system and method.
It is a further object of the invention to provide a trace system and method which provides for capture of processor bus and I/O bus behavior.
It is a further object of the invention enable development of computer designs having high performance.
It is a further object of the invention to provide off-chip storage of trace data which does not reserve and consume chip I/Os for problem debug.
It is a further object of the invention to provide a trace mechanism which is capable of tracing many facilities each hardware cycle.
It is a further object of the invention to provide a target system under test which stores trace signals to main store, the trace signals in main store thereafter being available for access and analysis by any mechanism which is capable of accessing main store, such as an I/O device, a target processor, or another processor.
It is a further object of the invention to provide a hardware tracing system which does not require the insertion of software trace instructions into the instruction stream.
SUMMARY OF THE INVENTION
In accordance with the invention, a system and method is provided for capturing trace data in main store. Trace data signals are captured and driven to a trace array for storage. In accordance with a first embodiment, responsive to the trace array becoming full, further trace signal capture is disabled and the contents of the trace array are moved to main store. In accordance with a second embodiment, the contents of the trace array are moved to main store when a storage request queue is empty.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
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Beckstrand Shelley M
Mai Rijue
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