Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-03
2005-05-03
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S001000, C703S013000, C703S014000
Reexamination Certificate
active
06889366
ABSTRACT:
The present invention is directed to a system and method for coevolutionary circuit design. A system suitable for providing integrated circuit design may include a memory suitable for storing a first set of instructions and a second set of instructions and a processor communicatively coupled to the memory. The processor is suitable for performing the first set of instructions and the second set of instructions. The first set of instructions is suitable for configuring a processor to provide an integrated circuit development environment in which a support methodology for an integrated circuit is created. The second set of instructions is suitable for configuring a processor to provide tools for implementing a platform architecture of an integrated circuit in which the platform architecture supplies a structure of the integrated circuit. The first set of instructions and the second set of instructions are linked through at least one formalism so that at least one of an action taken utilizing the platform architecture influences the support methodology and an action taken utilizing the support methodology influences the platform architecture.
REFERENCES:
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 5615124 (1997-03-01), Hemmi et al.
patent: 5742738 (1998-04-01), Koza et al.
patent: 5818728 (1998-10-01), Yoeli et al.
patent: 5818729 (1998-10-01), Wang et al.
patent: 6058385 (2000-05-01), Koza et al.
patent: 6269277 (2001-07-01), Hershenson et al.
patent: 6459136 (2002-10-01), Amarilio et al.
patent: 20030097241 (2003-05-01), Koford et al.
patent: 01202397 (2001-07-01), None
patent: 02202886 (2002-07-01), None
O. Hammi et al., CoEvolvable Hardware Platform for Automatic Hardware Design of Neural Networks, Proceedings of IEEE International Conference on Industrial Technology, vol. 1, pp. 509-513, Jan. 2000.*
X. Yao, Following the Path of Evolvable Hardware, Communications of the ACM, vol. 42, Issue 4, pp. 47-49, Apr. 1999.*
M. Shipper et al., Quo Vadis Evolvable Hardware, Communications of the ACM, vol. 42 Issue 4, pp. 50-59, Apr. 1999.*
J. Mizoguchi et al., Production Genetic Algorithms for Automated Hardware Design Through an Evolutinary Process, IEEE World Congress on Computational Intelligence, Proceedings of the First IEEE Conference on Evolutionary Computation, pp. 661-664, Jun. 1994.*
“Self-Reconfigurable Programmable Logic Device” by Reetinder Sidhu, et al.: File # 3115; University of Southern California, Office of Technology Licensing, Los Angeles, CA; www.usc.edu/academe/otl; Sep. 7, 2001.
LSI Logic Corporation
Suiter - West PC LLO
Thompson A. M.
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