Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2002-05-29
2008-10-28
Smithers, Matthew (Department: 2137)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S144000
Reexamination Certificate
active
07444476
ABSTRACT:
A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the device. A password for providing full communication in the data path is stored in a defined location in the memory. Upon reading the memory location, the password is provided to a code security module. The password provided to the code security module is compared to a data string provided by the user. If the password and the data string match, the password data path is open for communication between the memory and the processor core. If the password and data string do not match, the password data path is closed to communication between the memory and the processor core.
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G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas, “Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions”, May 2005, ACM SIGARCH Computer Architecture news, vol. 33 Issue 2, pp. 1-12.
English Translation of JP 2002082902 A has been provided on Jul. 1, 2008, pp. 1-7.
Foley David P.
Gnanasabapathy Thiru
Brady W. James
Fields Courtney D
Marshall, Jr. Robert D.
Smithers Matthew
Telecky , Jr. Frederick J.
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