System and method for clock synchronization of multi-channel...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S356000, C327S155000

Reexamination Certificate

active

07110485

ABSTRACT:
A clock control circuit for use in a multi-channel baud-rate timing recovery loop includes a control circuit responsive to a phase error signal from at least one phase detector for generating at least one clock control signal, wherein said control circuit propagates adjustments required for frequency correction in a synchronous fashion across all of the N-channels.

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patent: 901126 (1999-03-01), None
Hatamian, et al., “Design Considerations for Gigabit Ethernet 1000Base-T Twisted Pair Transceivers,” Custom Integrated Circuits Conference 1998; Proceedings of the IEEE 1998 Santa Clara, CA, US, May 11-14, 1998, New York, US, pp. 335-342, dated May 11, 1998, XP010293978, ISBN: 0-7803-4292-5.
European Search Report, EP 03 25 5932, dated Sep. 28, 2005.

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