Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2008-12-17
2011-11-08
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S100000, C716S101000, C716S103000, C716S104000, C716S111000, C716S123000, C716S132000, C716S133000, C703S002000, C703S014000
Reexamination Certificate
active
08056045
ABSTRACT:
In a circuit simulation system, a storage section is configured to store a circuit data, an analysis condition data and an output data. An initial data setting section reads out the circuit data and the analysis condition data from the storage section and sets an initial data and a convergence condition for a solution calculating process based on the circuit data and the analysis condition data. A processing section generates a circuit equation to each of a voltage variable and a current variable based on the circuit data, and executes the solution calculating process based on the initial data to calculate a solution. A convergence determining section executes a convergence determining process of whether or not the solution meets the convergence condition, on the voltage variable. An output section stores the solution into the output data when it is determined to meet the convergence condition. A repetition control section controls the processing section to calculate a next solution by using the solution as the initial data, when it is determined not to meet the convergence condition.
REFERENCES:
patent: 5963724 (1999-10-01), Mantooth et al.
patent: 6236956 (2001-05-01), Mantooth et al.
patent: 7085700 (2006-08-01), O'Riordan et al.
patent: 7236895 (2007-06-01), Sagesaka et al.
patent: 7606693 (2009-10-01), Jeng et al.
patent: 7813884 (2010-10-01), Chu et al.
patent: 2001/0026292 (2001-10-01), Ishizaki
patent: 2006/0095218 (2006-05-01), Sagesaka et al.
patent: 2006/0282239 (2006-12-01), Chu et al.
patent: 2008/0010329 (2008-01-01), Kuwada
patent: 10-222555 (1998-08-01), None
patent: 11-110420 (1999-04-01), None
patent: 2006-133994 (2006-05-01), None
Zhang et al.; “Research on Three-Phase Voltage-Source Selective Harmonic Elimination Inverter”; Publication Year: 2005; Transmission and Distribution Conference and Exhibition: Asia and Pacific, 2005 IEEE/PES; pp. 1-4.
Wu et al.; “New approaches in a 3-D one-carrier device solver”; Publication Year: 1989; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on; vol. 8 , Issue: 5 pp. 528-537.
Ng, S.W.; “Application of the variable dimension Newton method to large scale circuits”; Publication Year: 1998; Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on; vol. 6; pp. 223-226 vol. 6.
The Donald O. Pederson Center for Electronic Systems Design SPICE (http://embedded.eecs.berkeley.edu/pubs/downloads/spice/index.htm) Dec. 26, 2007.
McGinn IP Law Group PLLC
Renesas Electronics Corporation
Rossoshek Helen
LandOfFree
System and method for circuit simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for circuit simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for circuit simulation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4262028