Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-01-07
2004-06-15
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
26, 26
Reexamination Certificate
active
06751146
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory. Specifically, the present invention relates to a system and method for restoring charge lost from a charge storage element in a non-volatile memory.
BACKGROUND ART
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage
on-volatile medium so that the data and computer programs is not lost when power is removed.
Flash memory (or Flash RAM) is an example of a non-volatile memory device. Flash memory devices use a memory cell transistor with a floating gate structure. The typical memory cell in a flash memory device comprises an access transistor and a storage element, such as a floating gale. Data in the flash memory device are programmed or erased by accumulation or depletion of charge, respectively, across a thin insulating film between a substrate and a storage element (e.g., floating gate). Programming of the memory cells occurs by applying a sufficient voltage difference to the transistors to cause excess electrons to accumulate on the storage element. Erasure of the memory cell is done by applying a voltage difference that causes the charge on the storage element to be extracted.
Prior Art
FIG. 1A
shows a diagram of a typical memory cell with a floating gate
120
. A source
130
and drain
135
are fabricated in a substrate
105
, and separated from the floating gate
140
by an oxide
125
. The control gate
110
is separated from the floating gate by an oxide
115
. In writing to the memory cell, a charge
140
is transferred across the oxide
125
into the floating gate
140
. The charge transfer may be effected by either Fowler-Nordheim tunneling or channel hot electron injection. The memory cell of
FIG. 1A
may be used to store multiple bits of information by injecting different amounts of charge. In the floating gate, the charge is mobile and not localized.
Prior Art
FIG. 1B
shows a diagram of another memory cell structure that replaces the floating gate
140
of
FIG. 1A
with a dielectric storage element
160
. The dielectric storage element
160
may be injected with two distinct charges
175
, each located near a symmetric drain/source
170
. In contrast to the floating gate in which different bits (or combinations of bits) are associated with a charge level, the dielectric charge storage element provides for the representation of bits through discrete localized charges. The control gate
150
, oxide
155
, oxide
165
and substrate
145
are similar to the control gate
110
, oxide
115
, oxide
125
and substrate
105
of FIG.
1
A.
Prior Art
FIG. 2
shows a diagram
200
for the threshold voltage of a multi-level (or multi-bit) memory cell array. The example shown in
FIG. 2
corresponds to a two-bit memory cell that has four nominal threshold voltages (V
T11
, V
T10
, V
T01
, and V
T00
,) associated with four possible logical bit combinations (11, 10, 01, and 00). The association between logical values and threshold values is arbitrary. In a memory cell array, or large population of memory cells, each group of cells associated with a logical value will have a distribution of threshold values distributed about the nominal threshold value (V
T
). Distributions
205
,
210
,
215
, and
220
correspond to threshold voltages V
T11
, V
T10
, V
T01
, and V
T00
, respectively. N represents the number of cells as a function of the threshold voltage V
T
.
In order for the logical values in a multi-level memory cell to be distinguishable, they must be separated by a read margin M. In the multi-level example of
FIG. 2
, distributions
205
and
210
are separated by read margin M
1
, distributions
210
and
215
by M
2
, and distributions
215
and
220
by M
3
. The width of the distribution for a threshold voltage is in part a function of geometry and process variations, and defects.
A fundamental difference between dynamic random access memory (DRAM) and similar memory types is that non-volatile memory cells such as those shown in
FIGS. 1A and 1B
is that they are programmed by transferring charge across a dielectric layer, whereas DRAM memory cells are programmed by charging a capacitor through a transistor switch. The leakage characteristic of DRAM cells requires that the cells be refreshed on a regular basis, whereas non-volatile memory cells are designed to maintain their programmed state virtually indefinitely, without refresh, hence the name “non-volatile memory.”
Although fundamental properties of the materials used to fabricate non-volatile memory cells provide a basis for fabricating highly stable non-volatile memory devices, the quest for smaller device geometries and higher information densities has resulted in a reduction in the margin of stability for many devices at high write/erase cycle counts and at high temperatures. This trend is expected to continue as critical dimensions for photolithographic processes continue to decrease, and thinner films arc employed to reduce working voltages.
Even high quality dielectric films are susceptible to tunneling and thermally assisted conduction if they are made thin enough, and charge losses that were previously expected to occur on a geologic time scale, even at elevated temperatures, are now within the realm of normal operating conditions and lifetimes. The loss of ability of a memory cell to retain charge is manifested in shifting threshold voltages and compromised read margins. What is needed is a method for offsetting threshold voltage shifts and maintaining read margins.
DISCLOSURE OF THE INVENTION
A non-volatile memory device comprising logic for charge restoration is disclosed. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.
In a method embodiment of the present invention, boundary values are established for the allowable range of threshold voltages associated with each logical value of a memory cell. These boundary values define the read margins between logical values/threshold voltage values for the memory cell, and are related to the distribution of threshold voltages for the population (e.g., array) to which the memory cell belongs. Periodically, a memory cell is selected from the array and read to determine a value. The read value is compared to at least one boundary to determine whether the cell value has drifted into a margin. In the event that the memory cell value has drifted into a margin, a write procedure is performed to push the cell threshold value back across the boundary.
In another embodiment of the present invention, a non-volatile memory device includes restore logic coupled to read and write circuits for sensing and altering the state of memory cells belonging to an array of memory cells. The read and write circuits are coupled to decoder circuits for selecting a memory cell from the array of memory cells. The restore logic may include a processor for performing a statistical analysis on the memory cell array. Certain memory cells within the memory cell array may be reserved for use by the re
Khan Imran
Wang Jianshi
Wang Zhigang
Advanced Micro Devices , Inc.
Le Vu A.
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