System and method for calculating effective capacitance for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06925623

ABSTRACT:
A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an effective capacitance of the interconnect model to be inversely proportional to a voltage at the driving point node of the interconnect model; and storing the value of the effective capacitance. Such a method can be used to calculate effective capacitance of the interconnect model using analytical techniques.

REFERENCES:
patent: 6314546 (2001-11-01), Muddu
patent: 6601223 (2003-07-01), Puri et al.
patent: 6721929 (2004-04-01), Li et al.
Andrew B. Kahng and Sudhakar Muddu,Proc. IEEE Intl. Conf. on VLSI Design, “Improved Effective Capacitance Computations For Use In Logic And Layout Optimization,” 1999 pp. 578-582.
Kanak Agarwal, Dennis Sylvester and David Blaauw,Design Automation Conference(DAC)'03, “An Effective Capacitance Based Driver Output Model For On-Chip RLC Interconnects,” Jun. 2-6, 2003, pp. 376-381.
Azeez J. Bhavnagarwala and James D. Meindl,Techon 2000, “Interconnect Delay Models For Arbitrary Wire-Tree Networks,” Microelectronics Research Center and the School of Elec. And Comp. Eng., Georgia Inst. Of Tech., Atlanta, GA.

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