Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-08-23
2005-08-23
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S119000, C711S122000, C711S141000, C709S241000, C709S241000
Reexamination Certificate
active
06934813
ABSTRACT:
In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.
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Dinh Ngoc V
Fish & Neave IP Group of Ropes & Gray LLP
Ingerman Jeffrey H.
Micro)n Technology, Inc.
Sparks Donald
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