Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-03-13
2003-10-21
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S118000, C711S119000, C711S122000, C704SE21020, C704SE21020
Reexamination Certificate
active
06636946
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the processing of memory requests in a computer system. More particularly, this invention relates to the caching of data based on the identity of the system resource making the memory request.
It is known to provide cache in computer systems to minimize the effects of memory latency. If the results of memory requests that are made frequently are stored in a cache memory adjacent to a central processing unit (CPU), the time necessary for any of those memory requests to be fulfilled is reduced. Thus, for example, in the case of a microprocessor used as the CPU in a personal computer, cache memory may advantageously be provided on-board the microprocessor chip, or in the core logic chipset that includes the microprocessor.
As memory has become less expensive and more available, additional and larger caches have become possible. Thus, in addition to the cache described above, which has come to be known as level-one, or L1, cache, it is known to provide level-two, or L2, cache at a somewhat greater distance from the CPU than the L1 cache; typically, L2 cache is also larger than the L1 cache. Because L2 cache is farther from the CPU than L1 cache, it may take longer for the CPU to access the L2 cache than the L1 cache. Moreover, because L2 cache is not expected to be as fast as L1 cache, the memory devices used for L2 cache may be slower than those used for L1 cache. As a result, L2 cache is used for the results of requests that are made less often, or whose arrival at the CPU is not as time critical.
It has now become known as well to provide a level-three, or L3, cache at an even greater distance from the CPU, either within the core logic chipset or elsewhere in the system (e.g., in the case of personal computer, on the motherboard).
L1 and, to some extent, L2, caches have been used primarily to cache memory requests made by the CPU itself. This has been because, first, it is axiomatic that CPU operation is central to all other system operations; if the CPU is slowed down, it cannot perform operations and direct other parts of the system. Second, cache size has heretofore been limited, and the results of CPU memory requests are typically small enough to fit within previously available caches.
When only CPU memory requests were cached, it normally was not necessary to determine whether or not a particular request should be cached. The results of all requests were typically cached, and logic, such as a least-recently-used routine, was used to determine, when the cache was full, which cached item should be deleted to make room for the next item to be cached.
With the advent of larger caches, such as those available as L3 cache, the caching of results of memory requests made by other system components such as input/output (I/O) components, which results tend to be larger than those of requests made by the CPU, becomes possible. However, if one is going to cache the results of memory requests by various system components, which are of less importance than the CPU, and which vary among themselves in level of importance, it becomes necessary to distinguish between requests whose results are to be cached and requests whose results are not to be cached.
SUMMARY OF THE INVENTION
In accordance with the present invention, caching decisions are facilitated by associating with each memory request an identification, or tag, of the system component that is the source of the memory request. The source tag can be used by the cache control logic to determine whether or not the results of a particular request should be cached. The cache control logic may be programmed to always, or never, cache the results of memory requests by particular components.
While the cache control logic could be fixed, an algorithm, similar to the least-recently-used routine referred to above, can be used to rewrite the cache control logic on the fly based on system conditions and changing memory usage patterns.
Thus, in accordance with the invention, a method is provided for caching data retrieved from memory in response to a request by a system resource in a computer system. Under the method, when a memory request is received from the system resource, a source tag, identifying the system resource, is appended to the memory request. The memory request is processed to determine, based on the source tag, whether the result of the memory request is to be cached.
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Dinh Ngoc
Fish & Neave
Ingerman Jeffrey H.
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