System and method for caching

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S132000

Reexamination Certificate

active

10294091

ABSTRACT:
Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

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Jim Handy, “The Cache Memory Book: the authoritative reference on the cache design,” □□Academic Press, Inc., Second edition, 1998. □□pp. 18, 64-66.
Tse et al., “CPU Cache Prefecting: timing Evaluation of Hardware Implementations,” IEEE Transactions on Computers, vol. 47, No. 5, May 1998, pp. 509-526.

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