Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-12-19
2010-11-16
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S119000, C711S124000, C711S134000, C711S136000, C711S141000, C711S159000, C711S160000
Reexamination Certificate
active
07836257
ABSTRACT:
A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.
REFERENCES:
patent: 6185658 (2001-02-01), Arimilli et al.
patent: 6247098 (2001-06-01), Arimilli et al.
patent: 6385695 (2002-05-01), Arimilli et al.
patent: 6460114 (2002-10-01), Jeddeloh
patent: 6970976 (2005-11-01), Arimilli et al.
patent: 7076609 (2006-07-01), Garg et al.
patent: 7277992 (2007-10-01), Shannon et al.
patent: 2006/0123206 (2006-06-01), Barrett et al.
patent: 2006/0179235 (2006-08-01), Bell, Jr. et al.
patent: 2006/0179250 (2006-08-01), Guthrie et al.
patent: 2006/0184742 (2006-08-01), Clark et al.
patent: 2006/0184743 (2006-08-01), Guthrie et al.
patent: 2006/0230252 (2006-10-01), Dombrowski et al.
patent: 2006/0236037 (2006-10-01), Guthrie et al.
Speight, Evan et al., Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors, International Conference on Computer Architecture; Proceedings of the 32nd Annual International Symposium on Computer Architecture, 2005, pp. 346-356.
Zhang, Michael et al., Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors, International Conference on Computer Architecture; Proceedings of the 32nd Annual International Symposium on Computer Architecture, 2005, pp. 336-345.
Memik, Gokhan et al., Reducing energy and delay using efficient victim caches, International Symposium on Low Power Electronics and Design; Proceedings of the 2003 international symposium on Low power electronics and design; Seoul, Korea; Session: Power efficient cache design, 2003, pp. 262-265.
Allu, Bramha et al., Exploiting the replication cache to improve performance for multiple-issue microprocessors, ACM SIGARCH Computer Architecture News archive; vol. 33 , Issue 3 Special issue: MEDEA 2004 workshop; Column: Regular contributions, 2005, pp. 63-71.
Naz, Afrin et al., Making a case for split data caches for embedded applications, Memory Performance: Dealing With Applications, Systems And Architecture; Proceedings of the 2005 workshop on Memory performance: Dealing with Applications , systems and architecture; Saint Louis, Missouri; Special Issue: MEDEA'05, 2006, pp. 19-26.
Dybdahl, Haakon et al., An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, Memory Performance: Dealing With Applications, Systems And Architecture, Proceedings of the 2005 workshop on Memory performance: Dealing with Applications, 2006, pp. 45-52.
Temam, Oliver, Investigating optimal local memory performance, Architectural Support for Programming Languages and Operating Systems; Proceedings of the eighth international conference on Architectural support for programming languages and operating systems; San Jose, California, United States, 1998, pp. 218-227.
Cox Jason Alan
Dorsey Robert John
Le Hien Minh
Nicholas Richard
Robinson Eric Francis
Caldwell, Esq. Patrick E.
International Business Machines Corpation
Savla Arpan P.
Shah Sanjiv
The Caldwell Firm, LLC
LandOfFree
System and method for cache line replacement selection in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for cache line replacement selection in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for cache line replacement selection in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4166259