System and method for cache coherency in a cache with...

Details System and method for cache coherency in a cache with... System and method for cache coherency in a cache with...

2004-12-27

2008-11-18

Ellis, Kevin (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C707S793000, C710S107000

Reexamination Certificate

active

07454576

ABSTRACT:
A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.

REFERENCES:
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patent: 6260114 (2001-07-01), Schug
patent: 6393521 (2002-05-01), Fujii
patent: 6408365 (2002-06-01), Hosomi
patent: 7111128 (2006-09-01), Hum et al.
patent: 2004/0039879 (2004-02-01), Gaither
patent: 2006/0143404 (2006-06-01), Chen et al.
Int'l Application No. PCT/US2005/047595 Int'l Search Report & Weritten Opinion mailed Jul. 18, 2006.

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