Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-09-12
2002-03-12
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S108000, C710S108000, C439S082000
Reexamination Certificate
active
06356966
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to Compact Peripheral Component Interconnect (cPCI) bus architecture and, more particularly, to systems for bridging cPCI bus segments on a backplane and coupling Single Board Computers (SBCs) to the backplane.
BACKGROUND OF THE INVENTION
PCI (Peripheral Component Interconnect) is the dominant bus architecture for computers that are based upon Intel and comparable microprocessors. This architecture is used in several applications including PC motherboards, passive backplane systems, and CompactPCI (cPCI). The PCI architecture is limited in terms of the number of PCI load devices on expansion boards that any given bus segment can support. When an application requires more expansion devices than a given bus segment can support, the use of a PCI to PCI Bridge is required. The PCI to PCI Bridge acts as a repeater and amplifies the bus signals so that the bus signals can be provided to additional expansion devices. For passive backplane architecture, the addition of a bridge to the backplane is relatively simple. Usually, there is ample space on the backplane itself to place the bridge components and to route the traces necessary for proper connection of the bridge to the remainder of the backplane. For cPCI architecture, however, where the number of slots that are available on the backplane for coupling devices to the backplane is a valuable feature and active circuitry on the backplane is discouraged, insufficient room exists on the backplane to place bridge components on the backplane itself.
At least two strategies are currently known for adding a bridge to a backplane having cPCI architecture. Both of these strategies involve placing the bridge components on a daughter board that plugs into the backplane. Referring to
FIG. 1
, one prior art system employs a single circuit board
20
with bridging components that connects at two points to a backplane
10
having multiple slots
12
(pins in slots not shown) including slots
12
a
-
12
h
. Specifically, the circuit board
20
connects to the rear of the backplane
10
at two of the slots
12
d
and
12
h
, and is mounted parallel to the backplane between those slots. Because the circuit board
20
connects to two separate slots
12
d
and
12
h
, which in the embodiment of
FIG. 1
are positioned four slots apart from one another, this bridge implementation is commonly termed a “mezzanine bridge”. Turning to
FIGS. 2 and 3
, a second known system for bridging bus segments on a backplane having cPCI architecture employs one or more circuit boards
30
that extend from the backplane
10
at right angles to the backplane. The one or more circuit boards
30
can plug into the backplane
10
from either the front or rear of the backplane. This bridge implementation can be termed a “plug-in card bridge”.
Although both of these bridge systems provide functional bus expansion, both systems have significant undesirable effects. First, both systems reduce the total number of slots that are available on a backplane for connection to expansion devices. This is due to the nature of cPCI architecture. In accordance with cPCI architecture, the backplane
10
must have a system slot followed by
1
to
7
expansion slots. For example, with reference to
FIG. 1
, the backplane
10
includes a system slot
12
a
followed by
7
successive expansion slots
12
b
-
12
h
. The system slot
12
a
is the location at which a system board, usually a Single Board Computer (SBC) which has the main system processor, is connected to the backplane
10
. The system slot
12
a
is unique from the other slots in that all bus clocks, bus requests, bus grants, and other bus control signals originate at the system slot. Only the main system processor can be installed into the system slot
12
a.
As shown in
FIG. 1
, the circuit board
20
of the mezzanine bridge receives bus signals from the backplane
10
at slot
12
d
and outputs bus signals into the rear of the backplane slot
12
h
. Consequently, slot
12
h
effectively becomes a new system slot and cannot be connected to any expansion device. As a result, one expansion slot position is always lost when a mezzanine bridge is employed. A reduction in the number of available expansion slots can likewise occur when a plug-in card bridge is employed. Typically, at least one slot and sometimes two slots are required to accommodate the bridging board or boards in the plug-in card bridge implementation. For applications in which a maximum “board to slot” count is required, these reductions in the number of available expansion slots on the backplane
10
due to bridging are not acceptable.
In addition to reducing the number of expansion devices that can be connected to a given backplane, both of the conventional strategies for bridging bus segments on a backplane compromise the input/output (I/O) possibilities of the cPCI architecture. Typically, the cPCI architecture allows “pass through” I/O from boards that are connected to the slots
12
on the front of the backplane
10
, to plug-in I/O transition boards connected to the rear of the backplane. However, when a mezzanine bridge is used, several slots typically become unavailable for use with the rear I/O transition boards. For example, in the embodiment shown in
FIG. 1
, four slots
12
d
-
12
g
that could potentially be used for I/O transition boards are lost due to the positioning of the circuit board
20
. In the case of the plug-in card bridge implementations of
FIGS. 2 and 3
, each of the slots
12
at which a circuit board
30
is connected to the backplane
10
is lost for use with
110
transitioning boards. That is, one slot is lost with the embodiment shown in
FIG. 2
, and two slots are lost with the embodiment shown in FIG.
3
.
The bridging of backplanes is only one situation in which the availability of slots of backplanes using the cPCI architecture is undesirably reduced. A similarly undesirable result occurs when it is necessary to connect a Single Board Computer (SBC) to a backplane and interface the SBC to multiple cPCI bus segments. Although the embodiment of
FIG. 4
shows the SBC
40
to be coupled to four connectors
14
a
,
14
b
,
14
d
and
14
e
that are positioned along the single slot
12
h,
in alternate embodiments the SBC is coupled to two pairs of the connectors
14
that are positioned on two adjacent slots, e.g., connectors
14
a
and
14
b
of each of slots
12
g
and
12
h.
Each of the conventional strategies for attaching an SBC to a backplane can undesirably limit the slots that are available for connecting expansion devices to the backplane. Typically the SBC
40
has a significant width due to the CPU
42
, which results in the SBC blocking access to one or more adjacent slots. For example, with reference to the embodiment shown in
FIG. 4
, the SBC
40
blocks access to slot
12
g
due to the width of the CPU
42
. Further, in certain embodiments a daughter board (not shown) must additionally be coupled to the SBC
40
in order to allow proper routing of signals. The existence of the daughter board also results in an increased overall width of the SBC assembly such that access to an additional adjacent slot, e.g., slot
12
i,
is blocked.
The conventional strategies for attaching an SBC have other undesirable characteristics as well. For example, the SBC
40
of
FIG. 4
requires at least five inches of extra trace length in the backplane for the second bus segment. This violates the 7.3″ trace length limit stated in the PCI Industrial Computers Manufacturers Group (PICMG) 2.0 R2.1 and R3.0 specifications for trace length for cPCI bus segments. Further, the configuration of the SBC
40
of
FIG. 4
precludes the use of the upper two connectors for rear I/O. Additionally, in the case of an SBC assembly that includes a daughter board, the SBC assembly suffers from additional increased exposure to interference due to the impedance of stubs (not shown) that typically exist on the daughter board.
Therefore, it would be advantageous if a new system and method were de
Loach Charles A
Yutkus Julian J.
APW Ltd.
Dharia Rupal
Quarles & Brady LLP
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