Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration – Loading initialization program
Reexamination Certificate
2000-07-21
2001-10-09
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
Loading initialization program
Reexamination Certificate
active
06301657
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to microcomputers.
BACKGROUND OF THE INVENTION
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network including for example connection to a host microcomputer for use in debugging routines. Such systems are known in which each of the interconnected microcomputer chips has its own local memory. Such microcomputers may have the operation of the CPU suspended without resetting state on the chip. Alternatively they may undergo a reset operation which resets all circuitry on the chip. In this case boot code is required to resume CPU operation.
It is an object of the present invention to provide an improved microcomputer, and an improved method of operating a microcomputer system, in which external communications are simplified and boot code can be obtained from locations off-chip.
SUMMARY OF THE INVENTION
The invention provides a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said integrated circuit device further comprising an external port connected to said bus on the integrated circuit chip and to an external computer device having a second memory, said external computer device being operable to transmit control signals through said port (a) to suspend execution by the CPU of instructions obtained from said first memory (b) to provide from said second memory boot code to be executed by the CPU and (c) to restart operation of the CPU using said boot code.
Preferably said CPU is provided with logic circuitry operable to suspend execution of an instruction sequence by said CPU, said logic circuitry having an address store for holding an instruction location address for use in resuming execution of an instruction by the CPU, said logic circuitry being connected to said communication bus whereby the logic circuitry may receive a signal packet from said external computer device through said port.
Preferably said CPU includes an instruction pointer circuit for indicating a next fetch address in execution of an instruction sequence and said address store of said logic circuitry is operable to change the pointer value in said instruction pointer circuit in response to a signal packet from said external computer device.
Preferably said single integrated circuit chip has a plurality of CPUs on the same chip each connected to said communication bus and to said external port.
The invention includes a method of booting a computer system which comprises a microprocessor on an integrated circuit chip with an on-chip CPU, a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to said CPU, said integrated circuit device having an external port connected to said bus and to an external computer device having a second memory, said method comprising transmitting control signals from said external device through said external port (a) suspending execution by the CPU of instructions obtained from said first memory (b) providing from said second memory boot code to be executed by the CPU and (c) restarting operation of the CPU using said boot code.
Preferably in response to control signals through said external port from said external computer device, logic circuitry connected to said on-chip CPU operates to suspend execution of an instruction sequence by said CPU, store in an address store for said CPU and instruction location address for use in resuming execution of instructions by the CPU and cause said CPU to resume execution using said boot code.
Preferably communications on said communication bus are effected in bit parallel format and said external port translates packets to a bit serial format.
Preferably said external computer device is arranged to transmit through said external port a signal to suspend operation of said CPU, transfer boot code from said second memory through said external port to said first memory, to provide through said external port an indication of the location of the boot code in said first memory and to restart operation of said CPU using said boot code.
Preferably said external computer device transmits through said external port a signal to suspend operation of the on-chip CPU, provides through said external port an indication of a memory address in said second memory in which boot code is located, and transmits through said external port a signal to the on-chip CPU to restart execution using boot code located in said second memory, whereby said on-chip CPU resumes execution fetching boot code from said second memory through said external port.
In some embodiments more than one CPU is provided on said chip, said external computer device being operable to suspend execution by each CPU on said chip, provide from said second memory boot code to be executed by a first CPU on said chip, transmit a control signal to maintain a second CPU in a suspended state, and restart execution of said first CPU using said boot code while said second CPU remains suspended.
Said first CPU may be used to provide boot code for said second CPU and restart execution of said second CPU after said first CPU has been restarted by said external computer device.
REFERENCES:
patent: 4172281 (1979-10-01), Gordon
patent: 5452339 (1995-09-01), Siu et al.
patent: 5588118 (1996-12-01), Mandava et al.
patent: 5835784 (1998-11-01), Gillespie et al.
patent: 5842011 (1998-11-01), Basu
patent: 0 636 976 (1995-02-01), None
patent: 0 636 973 (1995-02-01), None
patent: 0 652 516 (1995-05-01), None
patent: 0 720 092 (1996-07-01), None
patent: 0 762 277 (1997-03-01), None
Standard Search Report dated Sep. 23, 1997.
Byte, vol. 21, No. 4, Apr. 1996, p. 177/178 Hyde, J.,How to Make Pentium Pros Cooperate.
Edwards David Alan
Jones Andrew Michael
May Michael David
Butler Dennis M.
Galanthay Theodore E.
Morris James H.
STMicroelectronics Limited
Wolf Greenfield & Sacks P.C.
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