System and method for bonding wafers

Details System and method for bonding wafers System and method for bonding wafers

1998-07-29

2000-09-12

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257766, 257777, 438455, H01L 2130

Patent

active

061181811

ABSTRACT:
Two wafers are bonded together through an annealing process that maintains temperatures at CMOS compatible levels (i.e., below 500 degrees Celsius). A layer of palladium (Pd) is formed on a first wafer. Preferably an adhesion layer of chromium (Cr) attaches the palladium layer to the first wafer. The palladium layer is engaged with silicon (Si) from a second wafer, and the engaged wafers are annealed to form a palladium-silicide (PdSi) bond between the palladium layer of the first wafer and the silicon of the second wafer. In addition to bonding the first wafer to the second wafer, the palladium-silicon bond may be used to form an electrical connection between the two wafers so that circuits on both wafers may communicate to one another through the palladium-silicon bond.

REFERENCES:
patent: 4826787 (1989-05-01), Muto et al.
patent: 5048744 (1991-09-01), Chang et al.
patent: 5262347 (1993-11-01), Sands
patent: 5882992 (1999-03-01), Kobeda et al.

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