Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-12-12
2006-12-12
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S146000
Reexamination Certificate
active
07149852
ABSTRACT:
Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.
REFERENCES:
patent: 5802577 (1998-09-01), Bhat et al.
patent: 5829040 (1998-10-01), Son
patent: 5875467 (1999-02-01), Merchant
patent: 5875472 (1999-02-01), Bauman et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6108737 (2000-08-01), Sharma et al.
patent: 6345342 (2002-02-01), Arimilli et al.
patent: 6457100 (2002-09-01), Ignatowski et al.
patent: 6490661 (2002-12-01), Keller et al.
patent: 6631401 (2003-10-01), Keller et al.
patent: 2001/0034815 (2001-10-01), Dungan et al.
patent: 2002/0009095 (2002-01-01), Van Doren et al.
patent: 2002/0073071 (2002-06-01), Pong et al.
patent: 2003/0018739 (2003-01-01), Cypher et al.
patent: 2003/0140200 (2003-07-01), Jamil et al.
patent: 2003/0145136 (2003-07-01), Tierney et al.
patent: 2003/0195939 (2003-10-01), Edirisooriya et al.
patent: 2003/0200397 (2003-10-01), McAllister et al.
patent: 2004/0123052 (2004-06-01), Beers et al.
patent: 2005/0013294 (2005-01-01), Cypher
patent: 2005/0053057 (2005-03-01), Deneroff et al.
Scheurich et al., “The design of a lockup-free cache for high-performance multiprocessors”, Nov. 14-18, 1988 Supercomputing '88. [vol. 1]. Proceedings.pp. 352-359.
Laudon et al., “The SGI Origin: a ccNUMA highly scalable server”, 1997 International Conference on Computer Architecture pp. 241-251.
Handy, “The Cache Memory Book”, 1998, Academic Press 2nd ed, pp. 144-155.
Rajeev, Joshi, et al., “Checking Cache-Coherence Protocols with TLA+”, Kluwer Academic Publishers, 2003, pp. 1-8.
Martin, Milo M.K., et al., “Token Coherence: Decoupling Performance and Correctness”, ISCA-30, pp. 1-12, Jun. 9-11, 2003.
Acacio, Manuel E., et al., “Owner Prediction for Accelerating Cache-to-Cache Transfer Misses in a cc-NUMA Architecture”, IEEE 2002.
Gharachorloo, Kourosh, et al., “Architecture and Design of AlphaServer GS320”, Western Research Laboratory, date unknown.
Gharachorloo, Kourosh, et al., “Memory Consistency and Event Ordering In Scalable Shared-Memory Multiprocessors”, Computer Systems Laboratory, pp. 1-14, date unknown.
Steely, Jr. Simon C.
Tierney Gregory Edward
Van Doren Stephen R.
Baker Paul
Hewlett Packard Development Company, LP.
Padmanabhan Mano
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