System and method for blocking cache use during debugging

Details System and method for blocking cache use during debugging System and method for blocking cache use during debugging

2006-05-30

2006-05-30

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S138000, C711S144000, C711S145000, C711S152000, C714S030000, C714S031000, C714S037000, C714S038110

Reexamination Certificate

active

07055006

ABSTRACT:
A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also includes combinatorial logic operable to use the first and second flags to determine whether the cache is used during execution of at least one instruction by a processor. The first flag identifies that the cache is enabled and the second flag identifies that the use of the cache is blocked when the processor is operating in a debugging mode.

REFERENCES:
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5636363 (1997-06-01), Bourekas et al.
patent: 6314530 (2001-11-01), Mann
patent: 6397382 (2002-05-01), Dawson
patent: 6505309 (2003-01-01), Okabayashi et al.
patent: 6691207 (2004-02-01), Litt et al.

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