Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-10-09
2007-10-09
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S200000
Reexamination Certificate
active
11054850
ABSTRACT:
A hardware implemented method for writing data to a cache is provided. In this hardware implemented method, a Block Initializing Store (BIS) instruction is received to write the data from a processor core to a memory block. The BIS instruction includes the data from the processor core. Thereafter, a dummy read request is sent to a memory controller and known data is received from the memory controller without accessing a main memory. The known data is then written to the cache and, after the known data is written, the data from the processor core is written to the cache. A system and processor for writing data to the cache also are described.
REFERENCES:
patent: 6449700 (2002-09-01), Hagersten et al.
patent: 7017005 (2006-03-01), Stark
patent: 2003/0061457 (2003-03-01), Geiger et al.
patent: 2004/0218435 (2004-11-01), Takahashi et al.
Laudon James P.
Patel Sanjay
Sivaramakrishnan Ramaswamy
Vemula Sunil
Lo Kenneth M
Martine & Penilla & Gencarella LLP
Sough Hyung
Sun Microsystems Inc.
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