Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-04-10
2007-04-10
Fleming, Fritz (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S057000
Reexamination Certificate
active
10337833
ABSTRACT:
A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.
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Tierney Gregory E.
Van Doren Stephen R.
Fleming Fritz
Hewlett--Packard Development Company, L.P.
Martinez David
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