Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-12-12
2006-12-12
Ferris, Fred (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S012000, C703S014000, C703S016000, C703S017000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07149675
ABSTRACT:
A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.
REFERENCES:
patent: 5638381 (1997-06-01), Cho et al.
patent: 5754454 (1998-05-01), Pixley et al.
patent: 6035107 (2000-03-01), Kuehlmann et al.
patent: 6035109 (2000-03-01), Ashar et al.
patent: 6141633 (2000-10-01), Iwashita et al.
patent: 6163876 (2000-12-01), Ashar et al.
patent: 6247163 (2001-06-01), Burch et al.
patent: 6301687 (2001-10-01), Jain et al.
patent: 6496955 (2002-12-01), Chandra et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 6687882 (2004-02-01), McElvain et al.
“An Efficient Equivalence Checker for Combinational Circuits”, Matsunaga, DAC 96', ACM 1996.
Hulgaard et al.,Equivalence Checking of Combinational Circuits Using Boolean Expression Diagrams,Danish Technical Research Council.
Cornelis A.J. van Eijk,Formal Methods for the Verification of Digital Circuits,dissertation dated Sep. 9, 1997, Eindhoven University of Technology, Netherlands, pp. 1-144.
Doreswamy Kiran B.
Hoskote Yatin V.
Ferris Fred
Intel Corporation
Kenyon & Kenyon LLP
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