Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-11-06
2007-11-06
Ha, Dac (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S326000, C375S354000, C375S355000, C375S376000
Reexamination Certificate
active
10635309
ABSTRACT:
In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal. The slicer may also receive an offset control signal to automatically adjust the slicer offset voltage. A phase detector may be used to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal. The rising edge output signal may correspond to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal. The falling edge output signal may correspond to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal. A first feedback circuit may be used to phase-lock the recovered clock signal to the sliced data signal utilizing at least one of the rising edge output signal and the falling edge output signal. At least one of the rising edge output signal and the falling edge output signal may be configured in a second feedback circuit to generate the offset control signal.
REFERENCES:
patent: 4270183 (1981-05-01), Robinson et al.
patent: 4805198 (1989-02-01), Stern et al.
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5142555 (1992-08-01), Whiteside
patent: 5150386 (1992-09-01), Stern et al.
patent: 5329559 (1994-07-01), Wong et al.
patent: 5349612 (1994-09-01), Guo et al.
patent: 5400370 (1995-03-01), Guo
patent: 5459753 (1995-10-01), Co et al.
patent: 5515403 (1996-05-01), Sloan et al.
patent: 5533072 (1996-07-01), Georgiou et al.
patent: 5568526 (1996-10-01), Ferraiolo et al.
patent: 5587709 (1996-12-01), Jeong
patent: 5610952 (1997-03-01), Yamanaka et al.
patent: 5619541 (1997-04-01), Van Brunt et al.
patent: 5640523 (1997-06-01), Williams
patent: 5644605 (1997-07-01), Whiteside
patent: 5712580 (1998-01-01), Baumgartner et al.
patent: 5712884 (1998-01-01), Jeong
patent: 5764709 (1998-06-01), Whiteside
patent: 5832047 (1998-11-01), Ferraiolo et al.
patent: 6088415 (2000-07-01), Guadet
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6192092 (2001-02-01), Dizon et al.
patent: 6205191 (2001-03-01), Portmann et al.
patent: 6236696 (2001-05-01), Aoki et al.
patent: 6285726 (2001-09-01), Gaudet
patent: 6304623 (2001-10-01), Richards et al.
patent: 6516006 (2003-02-01), Walker et al.
patent: 6526109 (2003-02-01), Chang et al.
patent: 7136441 (2006-11-01), Iwata et al.
patent: 2003/0102928 (2003-06-01), d'Haene et al.
patent: 2003/0165207 (2003-09-01), Noguchi et al.
patent: 2004/0161070 (2004-08-01), Yin et al.
MAXIM application note 1130: Phase-lock Loop Applications Using the MAX9382, Jun. 26, 2002.
Franceschino et al., “An IF communication Circuit Tutorial”, Motorola Inc. 1996, Publication # AN1539, pp. 1-8.
Redd, Justin, “Synch and Clock Recovery—An Analog Guru Looks at Jitter”, Maxim Integrated Products, Sunnyvale, California, Aug. 27, 2001, pp. 1-10.
d'Haene Wesley C.
Gupta Atul K.
Gennum Corporation
Ha Dac
Jones Day
Wang Ted M.
LandOfFree
System and method for automatically correcting duty cycle... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for automatically correcting duty cycle..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for automatically correcting duty cycle... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3876801