System and method for automatic insertion of on-chip...

Details System and method for automatic insertion of on-chip... System and method for automatic insertion of on-chip...

2007-11-27

2007-11-27

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11054916

ABSTRACT:
A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.

REFERENCES:
patent: 6446016 (2002-09-01), Zhu
patent: 6665843 (2003-12-01), Klink et al.
patent: 6807656 (2004-10-01), Gradin et al.
patent: 2003/0088395 (2003-05-01), Frech et al.

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