System and method for asynchronous clock regeneration

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C713S500000, C713S501000, C713S503000, C713S600000, C713S601000, C365S211000

Reexamination Certificate

active

07818528

ABSTRACT:
The present invention is a method of asynchronous clock regeneration. The method includes synchronizing a first write pointer and a second write pointer, the first write pointer being an offline write pointer, the second write pointer being an online write pointer. The method further includes swapping at least one bit from the first write pointer with at least one bit of the second write pointer when the bits are static. The method further includes regenerating a DQS (Data Strobe Signal) clock.

REFERENCES:
patent: 5133062 (1992-07-01), Joshi et al.
patent: 6889334 (2005-05-01), Magro et al.
patent: 6956775 (2005-10-01), Thompson et al.
patent: 2005/0050375 (2005-03-01), Novak et al.

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