System and method for assigning addresses to memory devices

Details System and method for assigning addresses to memory devices System and method for assigning addresses to memory devices

1997-04-23

2001-01-16

Peikari, B. James (Department: 2752)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S202000, C711S148000

Reexamination Certificate

active

06175891

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory systems and in particular to memory systems having multiple memory devices and a controller for serial selection of the memory devices.
2. Description of Related Art
Data systems incorporating memory systems having multiple memory devices are well known. By way of example,
FIG. 1
depicts a simplified conventional memory system which includes a host device
20
, an address decoder
22
and memory devices
24
A and
24
B. The host device
22
may be a microprocessor and the memory devices
24
A and
24
B may be separate memory integrated circuits. An address bus
26
is used to provide addresses to an address decoder
22
and to the memory devices
24
A and
24
B. The address decoder
22
has two outputs connected to enable inputs of the memory devices
24
A and
24
B. Typically, the most significant bit(s) of the address are provided on the bus
26
to the decoder
22
, with the remaining address bits being provided to each of the memory devices.
When memory is to be accessed, the processor
20
causes the address decoder
22
to decode the most significant bit(s) of the memory address placed on an address bus
26
. The decoder
22
will select one of the two memory devices
24
A and
24
B by generating either signal Sel
0
or Sel
1
. The selected memory device will respond to the address presented to it on the address bus and the deselected memory device, which is disabled, will not respond. Although not shown, a data bus is used to transfer data between the memory devices and the processor
20
, with only the selected device outputting data to the data bus during memory read operations.
The approach depicted in
FIG. 1
is sometimes referred to as radial device selection where each memory device has a separate select input. This approach works well when relatively few memory devices are employed and where access speed, particularly random access speed, is important. However, if a large number of memory devices are used so that large amounts of data can be stored, the requirement of separate select lines for each memory device results in large memory boards and a relatively large pin count for the control logic circuitry. Thus, unless access speed is critical and a large number of memory devices are used, the radial device selection approach of
FIG. 1
is not ideal.
FIG. 2
shows an alternative prior art device selection technique, sometimes referred to as serial selection. Again, a host device
28
is used which is connected to several memory devices
30
A,
30
B and
30
C by way of a system bus
32
. The memory devices
30
A,
30
B and
30
C are usually implemented as separate integrated circuits. The system bus
32
includes memory address and memory data and various control signals so that each of the memory devices
30
A,
30
B
30
C receives the same addresses, data and other signals. Each memory device is preassigned a unique address so that only one device will be accessed by the host device
28
during a memory operation. Typically, the memory devices
30
A,
30
B and
30
C are assigned addresses by way of jumper or switch settings represented by elements
34
A,
34
B and
34
C.
The jumpers or switch settings represented by elements
34
A,
34
B and
34
C require appropriate hardware which increases costs and utilizes memory board space. In addition, if additional memory devices are to be added to a memory system, a user has to determine an appropriate address for the added devices. This determination requires that a user ascertain what address ranges are not available and which addresses are free to be assigned to the new memory devices. Thus, there is a distinct possibility for error.
The
FIG. 2
approach also requires that dedicated pins be provided on each of the integrated circuit memory devices
30
A,
30
B and
30
C to receive the jumper wires or switches for assigning the addresses. These pins increase the pin count for the integrated circuits thereby increasing the cost of the packaging for the devices and increasing the likelihood that there will be mechanical problems and manufacturing errors through soldering and the like. These extra pins are also subject to defects and increase the possibility of damage to the integrated circuits as a result of electrostatic discharge.
There is a need for a memory system which provides the advantages of serial selection techniques, but allows the addition of memory devices without introducing the possibility of user error when such devices are added. Further, there is a need for a system having a reduced pin count. The present invention provides this and other advantages as will be appreciated by those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
SUMMARY OF THE INVENTION
A memory system is disclosed which includes a memory controller and a plurality of separate memory devices. Each of the memory devices includes an array of memory cells, such as flash memory cells, and addressing circuitry for addressing the array of memory cells. The memory devices further include a bus interface and a command decoder which decodes commands at the interface. Those commands include an assign address command. The memory devices each have local address storage circuitry which stores a local address for the memory device.
The memory system includes a memory controller having a bus interface coupled to the bus interface of each of the memory devices. The memory controller provides a local address to each of the memory devices, with the local address being stored in the local address storage circuitry of memory devices. In order to store the local address in one of the devices, the controller will place the assign address command on the bus interface of the memory devices, with the command decoder of a selected one of the memory devices responding to the command by permitting the local address to be stored in the selected memory device.
Preferably, the memory controller generates a select signal output, with the memory devices each having a select signal input and a select signal output. The memory controller select signal output is coupled to the select signal input of a first one of the memory devices, with the select signal output of the first memory device being coupled to the select signal input of a second one of the memory devices. The remainder of the memory devices are connected in series in this manner. The local address is transferred to the first memory device after the memory controller causes the select signal input of the first device to go active. After, the transfer, the first memory device causes the select signal input of the second memory device to go active so that a local address can be transferred to the second device. This sequence will continue until all of the memory devices have been assigned a unique local address. The end of the sequence is communicated back to the memory controller when the select signal output of the last memory device goes active.
Once the memory devices have all be assigned local addresses, it is possible to perform memory operations, such as read, program and erase operations, on the individual memory devices.


REFERENCES:
patent: 5029209 (1991-07-01), Strong, Jr. et al.
patent: 5293498 (1994-03-01), Iwatsubo
patent: 5430859 (1995-07-01), Norman et al.
patent: 5627784 (1997-05-01), Roohparvar
patent: 5640332 (1997-06-01), Baker et al.
patent: 5687117 (1997-11-01), Chevallier et al.
patent: 5873123 (1999-02-01), Patel et al.
“Draft Standard for A High-Speed Memory Interface (SyncLink)”, Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, New York: Institute of Electrical and Electronics Engineers, Inc., 1-52, (1996).

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