Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-21
2004-12-14
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06832361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a system and method for analyzing power distribution in an integrated circuit and more particularly, to a system and method for analyzing power distribution by using static timing analysis to calculate current waveforms.
2. Description of the Related Art
FIG. 1
provides a graphical representation of current in a typical integrated circuit chip over time. As indicated in
FIG. 1
, the current in the circuit rises to a peak sometime after the clock edge, and then gradually tapers off to near zero until the next clock edge occurs (assuming complementary metal oxide semiconductor (CMOS) logic). The height of each peak is a function of the number, location, and type of circuits switching. These parameters are controlled by the logical function of the chip and the data being supplied to the chip and can change on each subsequent clock cycle.
One goal of chip design is to optimize the power distribution on the chip so that each circuit on the chip is supplied with optimum supply voltage during each clock cycle. Of course, insufficient supply voltage would make the circuit slow and, perhaps, inoperable. Designers, on the other hand, must be careful not to overdesign the power distribution to each circuit because this would result in unnecessary chip size and wiring congestion.
In addition, designers are under increasing demand to reduce operating power, especially with respect to application specific integrated circuits (ASICs) and other advanced types of chips. As a result, chips are being designed to operate with lower power supply voltages and, in turn, lower device turn-on voltages. This causes a problem, however, because, as the device threshold voltage (Vt) and power grid supply voltages (Vdd) are reduced, the ratios of noise voltages to Vt and Vdd increase because the noise levels do not scale down at the same rate as Vt and Vdd. Consequently, circuit sensitivity to noise is increased in these new chips.
On the other hand, designers are also required to increase performance. Conventionally, designers improved performance by increasing signal current levels and/or duty cycles. However, high current levels create local and often sizable resistive voltage drops in the power supply wiring. In addition, increasing signal current levels and/or duty cycles further exacerbates the noise problems experienced in smaller chips and may also prevent the full Vdd supply voltage from being available to power some of the circuits on the chip.
Conventionally, chip designers use two methods to address this supply noise problem in smaller integrated circuit chips. One method is to “over-design” the circuits and/or the power distribution to make them either more tolerant of noise or power drops. However, this typically results in lower performance and/or increased power consumption, chip area and chip cost. In addition, because noise sensitivity problems are often not realized until very late in the circuit design process and sometimes not until after the chips is actually fabricated, this method typically requires subsequent re-modeling/simulation and/or redesign activity which can be expensive and time consuming.
Another method uses a power distribution analysis to identify potential problem areas or “hot spots” in the circuit that would compromise the integrity of the design. However, power distribution on a chip depends upon when and/or whether the various circuits on the chip will switch, which designers typically have no way of knowing with certainty. Therefore, some designers assume that all circuits are switching at the same time, such as on a leading edge of a clock. Although this “worst case scenario” makes power distribution analysis relatively easy, it is not very accurate because many portions of the integrated circuit do not switch at the same time. Therefore, the results would overstate voltage drops causing the chip to be over-designed.
Other chip designers may predict which circuits on the chip are switching and when they are switching by simulating functional patterns through the chip logic and capturing information about current draw and timing. In other words, real pattern sets are run through the chip and the switching information that is produced is captured. This analysis may be performed by automated simulation analysis programs which currently exist.
However, numerous patterns are required here which makes analysis costly. In addition, in spite of the numerous patterns, it remains likely that the maximum pattern (i.e., the pattern resulting in the maximum current for the circuit) will not be identified. Furthermore, there inevitably will be patterns which were not conceived or impossible to generate that will cause more switching activity than modeled. Therefore, this analysis commonly results in long analysis or design times and missed design errors.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, an object of the present invention is to provide a fast and accurate method and system for analyzing power distribution in an integrated circuit.
The inventive method for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.
The inventive method may further include generating a pre-characterized cell library containing cell characterization data and using the cell characterization data to perform the static timing analysis. Such cell characterization data may include charge data, timing data, voltage data, temperature data, load data, input slew rate data, direct current data and process corner data.
The inventive method may further include physically designing the integrated circuit chip using the pre-characterized cell library. Further, parasitic resistors, capacitors and inductors may be extracted from the physical design of the chip to generate an extracted signal net information which may be used to perform the static timing analysis.
The inventive method may further include refining the physical design of the integrated circuit chip using the current waveform data.
Further, the static timing analysis in the inventive method may determine when current is required on the integrated circuit chip, the amount of current required on the integrated circuit chip, and where current is required on the chip.
Further, the inventive method may assume that every circuit on the integrated circuit chip switches within a given clock cycle. The static timing analysis may include disregarding circuits which cannot switch during a same time period. In addition, each of said time periods may be greater than or equal to a rise or fall time that captures 95% of signals on the integrated circuit chip.
The static timing analysis may further include assigning a charge used by a circuit to at least one time period, calculating node voltages for each time period, checking calculated node voltages against allowable limits, calculating current densities using the calculated node voltages, and checking the calculated node voltages against electromigration and local heating rules.
The calculated node voltages may further be back annotated so that the static timing analysis is performed using the calculated node voltages.
In another aspect, a system according to the present invention may include a chip design device for using precharacterized cell data to logically and physically design the integrated circuit chip, power grid extracting means, for inputting physical design data from the chip design means and generating extracted signal net information, and a static timing analysis tool, for inputting the extracted signal net information and the physical design data and generating current waveform data. The system may f
Cohn John Maxwell
Gould Scott Whitney
Rose Ronald Dennis
Wemple Ivan
Zuchowski Paul Steven
Bowers Brandon
International Business Machines - Corporation
Kotulak, Esq. Richard M.
McGinn & Gibb PLLC
Smith Matthew
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