Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-03-01
2005-03-01
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000, C710S311000, C710S306000, C710S314000, C710S031000, C710S038000
Reexamination Certificate
active
06862647
ABSTRACT:
A system and method for observing transactions on a packet bus is disclosed. In one embodiment, a computer system includes a plurality of input/output (I/O) nodes serially coupled to a processor. Each of the I/O nodes may be configured to operate in a first (normal) mode, and a second (analysis) mode. During the normal mode, packets may be selectively conveyed through an I/O tunnel in the I/O node, and particular packets may be selectively conveyed to a peripheral bus interface in the I/O node. In the analysis mode, electrical signals corresponding to packets conveyed through the I/O tunnel may be replicated on a peripheral bus coupled to the peripheral bus interface. No conversion from the packet bus protocol to the peripheral bus protocol. A signal analyzer may be coupled to the peripheral bus, thereby allowing observation of the electrical signals.
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Heter Erik A.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Myers Paul R.
Phan Raymond N
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