Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-06-20
2010-06-08
Fan, Chieh M (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S354000, C327S002000
Reexamination Certificate
active
07733999
ABSTRACT:
The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for removing network-induced clock jitter and wander that occurs in a transport network during asynchronous mapping techniques, bit and/or byte-stuffing techniques, or traditional pointer adjustment schemes associated with traditional PDH (pleisiosynchronous digital hierarchy), SDH (synchronous digital hierarchy), and packet-based networks. The timing recovery circuit may be implemented in a logic circuit such as programmable, digital FPGA (field programmable gate array) logic, or alternatively in standard cell or gate-array ASIC (application-specific integrated circuit) technology, or like logic circuit design.
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Brownlee John H.
Connolly Matthew W.
Mateosky John P.
Bernard Christopher L.
Brown Tyler S.
Ciena Corporation
Clements Bernard PLLC
Fan Chieh M
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