Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2011-03-15
2011-03-15
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S156000, C707S999102, C707S999202
Reexamination Certificate
active
07908456
ABSTRACT:
Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.
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Adi-Tabatabai Ali-Reza
Hertzberg Ben
Saha Bratin
Bacon Shireen Irani
Intel Corporation
Lane Jack A
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