System and method for alignment of integrated circuits multiple

Details System and method for alignment of integrated circuits multiple System and method for alignment of integrated circuits multiple

1995-01-05

1998-11-10

Moses, R. L.

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355 53, 355 54, 355 72, 356399, 356400, 356401, 356358, 356359, 356363, G01B 1100, G03B 2700

Patent

active

058351965

ABSTRACT:
An alignment system (30) is provided for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.

REFERENCES:
patent: 5005046 (1991-04-01), Hashimoto
patent: 5333050 (1994-07-01), Nose et al.
patent: 5438413 (1995-08-01), Mazor
patent: 5444538 (1995-08-01), Pellegrini

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