Computer graphics processing and selective visual display system – Computer graphic processing system – Interface
Patent
1998-08-18
2000-12-12
Tung, Kee M.
Computer graphics processing and selective visual display system
Computer graphic processing system
Interface
345521, 710128, 710129, 711 3, G06F 1314
Patent
active
06160562&
ABSTRACT:
A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An interface controller coupled between a peripheral bus (excluding the CPU local bus) determines if an address forwarded from a peripheral device is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If that address (i.e., target address) is not the first address (i.e., initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. An offset between the target address and the modified address is denoted as a count value. The initial address aligns the reads to a cacheline boundary and stores in successive order the quad words of the cacheline in the queue of the bus interface unit. Quad words arriving in the queue prior to a quad word attributed to the target address are discarded. This ensures the interface controller, and eventually the peripheral device, will read quad words in successive address order, and all subsequently read quad words will also be sent in successive order until the peripheral read transaction is complete.
REFERENCES:
patent: 5636354 (1997-06-01), Lear
patent: 5793693 (1998-08-01), Collins et al.
patent: 5915126 (1999-06-01), Maule et al.
Chin Kenneth T.
Coffee Clarence K.
Collins Michael J.
Johnson Jerome J.
Jones Phillip M.
Compaq Computer Corporation
Daffer Kevin L.
Tung Kee M.
LandOfFree
System and method for aligning an initial cache line of data rea does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for aligning an initial cache line of data rea, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for aligning an initial cache line of data rea will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-222470