Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-27
2002-04-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S018000
Reexamination Certificate
active
06370678
ABSTRACT:
BACKGROUND OF THE INVENTION
One of the most important advances in the area of electronic integrated circuit (IC) design over the past few years has been the development of logic synthesis as part of the overall IC design process. In a nutshell, logic synthesis allows IC designers to more fully utilize the ever-increasing number of transistors available in an IC while ignoring the tedious complexities associated with direct gate-level design. Thus, logic synthesis has allowed the designer to concentrate on the functionality of an IC while, at the same time, reducing its associated time-to-market.
As shown in
FIG. 1
, logic synthesis currently is a vital part of a typical IC design process
1
. An IC designer initially generates a high-level behavioral or register-transfer-level (RTL) description (step
100
) of the functionality of a proposed IC, which is normally written in a hardware design language (HDL), with VHDL and Verilog being the two most popular examples. Often, a functional simulation of the behavioral or RTL description is performed thereafter to determine if the circuit logically operates as was intended (step
110
). If this simulation (step
110
) yields no unpleasant surprises, the designer then uses a set of software tools that performs logic synthesis (step
120
) to transform the behavioral or RTL description into a schematic representation of circuit elements, such as logic gates, transistors, resistors, and the like, along with the associated logical connections between elements. The synthesized circuit elements and logical connections are then simulated once again (step
130
) at the logic gate level to check the operation of the circuit against previously specified voltage and timing constraints. If the gate-level simulation (step
130
) executes successfully, the schematic of circuit elements and connections is then passed to a “place-and-route” tool (step
140
), which determines the actual location of the circuit elements and connections within the space available on the IC. A final simulation (step
150
) is then performed, this time on the circuit generated by the place-and-route tool, in order to determine if the chip meets all functional and timing constraints, given the actual physical layout of the circuit.
As can be seen in
FIG. 1
, successful completion of a step of the IC design process brings the IC design one step closer to being a viable IC. Conversely, any problems or failures discovered in any of the steps results in some portion of the design process to be repeated. (
FIG. 1
indicates a few of the possible “repeating” paths.) In the past, a reasonable number of failures were expected early on in the process, such as during functional simulation (step
110
) or gate-level simulation (step
130
), with relatively few problems encountered at final simulation (step
150
).
However, with the decreasing size in the IC geometries being used, and the correspondingly higher number of transistors available on an IC, the standard design process described above has proven inadequate at times, with a significant number of IC failures not being discovered until final simulation (step
150
). This is especially problematic considering that the manufacturing process for the IC is oftentimes begun prior to final simulation, since that simulation (step
150
) is quite a time-consuming task due to the complex nature of the circuit models and current waveforms involved. Unlike before, when logic gate timing delays contributed the overwhelming majority of the overall timing delay of a signal, the latest advances in IC manufacturing technology have caused the connections between logic gates to be the single largest contributor to signal delay in most cases. Since the signal delay in a connection is dependent upon the length of that connection, the placement and routing of the connection must be known with a high degree of certainty in order to accurately model the signal delay involved. Unfortunately, under typical IC design process
1
, the place-and-route information is not known until well after the RTL design and synthesis steps have been performed.
Recently, companies such as Synopsis Inc. and Avant! Corporation have devised new IC design tool strategies to deal with this problem. Although the various strategies differ in the details, they basically involve the addition of “quick,” or non-final, types of synthesis and place-and-route functions earlier in the design process to determine within certain error limits the lengths of the interconnections in the IC. In
FIG. 2
, an updated IC design process
2
is shown, with a quick synthesis and place-and-route step (step
200
) essentially being added early in the design flow. (Frequently, the “quick” place-and-route function is termed “floorplanning”.) As a result, timing simulations at the gate level are carried out using preliminary physical layout information, thereby giving the IC designer greater confidence that the IC will actually perform as expected prior to final place-and-route. In other words, the “logical” design steps of RTL definition and logic synthesis are more tightly coupled with the “physical” design steps of placing and routing under updated IC design process
2
. Potential timing problems are thus discovered earlier in the design process, saving development time that would otherwise be wasted during place-and-route (step
140
) and final simulation (step
150
). Therefore, the problems involved with meeting timing constraints under the older process have been mitigated somewhat with the newer IC design approaches.
However, the latest advances in design methodology do not appear to address all of the problems associated with the typical separation of the logical and physical portions of IC design. For example, some currently available IC design tools allow analysis of the average magnitude of the loads placed on the on-chip power grid during the logical portion of the design cycle to determine power requirements for the various areas of the IC. However, the IC power supply circuitry, which includes both the on-chip power circuitry and the IC package power circuitry, is generally not taken into account during the design of the IC core logic. As a result, incompatibilities between the IC power supply circuitry and the IC core logic circuitry can cause problems not easily identified until final simulation (step
150
).
Even if fluctuations of the power supply at the pins of an IC package are insignificant, the power still has a significant amount of circuitry to traverse before it reaches the on-chip logic circuitry of an IC, as can be seen in the diagrammatic representation of FIG.
3
. More specifically, package power supply pins
320
, typically labeled VDD and GND, are the entry points of the power and ground connections into an IC package
300
. Ordinarily, on LSI components, multiple VDD and GND power supply pins
320
are supplied to allow a sufficient amount of current to pass between IC package
300
and a circuit board power supply circuit
310
to operate the chip properly. Power supply pins
320
are, in turn, connected to a package power supply circuit
330
, which is made up primarily of, but not limited to, a network of metal planes, grids, and bypass capacitors inside the IC package. Package power supply circuit
330
, in turn, provides power to an on-chip power supply circuit
340
, which is made up mainly of metal grids and more bypass capacitors. It is on-chip power supply circuit
340
that is attached via multiple connection points to an IC core logic circuit
350
, which performs the logical functions expected of the IC. As is well-known in the art, the bypass capacitors in package power supply circuit
330
and on-chip power supply circuit
340
are placed across the power and ground planes and grids to help stabilize the power supply voltage levels by providing charge during short time periods of high current demand by core logic circuit
350
.
As can be appreciated by someone of skill in the art, the IC designer pays much attention to the problem of provid
Garbowski Leigh Marie
Smith Matthew
Way Kyle J
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