Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-03-30
2001-07-17
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S360000, C375S361000, C375S373000, C375S376000
Reexamination Certificate
active
06263035
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of wireless communications, and more specifically to the field of adjusting a phase angle of a recovered data clock signal from a data signal.
In wireless communications, data signals are transmitted over the air in an analog format, typically encoded in such a manner that clocking information for the data is embedded into the data signals and is transmitted along with the data. A typical encoding scheme used is Manchester Encoding where a data transmission clock, operating at twice the frequency of the data signal's clock, is embedded into the data signal. The use of Manchester Encoding inserts a data transmission clock transition into the middle of each data signal period and thus allows the recovery of the transmission clock by processing the received data stream.
One method for recovering the transmission clock in a Manchester Encoded data sequence is to attempt to detect the clock transition in the middle of every data signal bit. This can be problematic due to the fact that depending on a particular bit pattern, each single data signal bit may possess two data transmission clock edge transitions. Also due to noise which is often injected onto the transmitted data signal, the clock transition may not be present in every data signal bit. Additionally, the transmission clock transition may not be sharp enough for the clock edge detection circuitry to detect the transition, or it may be too sharp of a transition and the clock edge detection circuitry cannot detect the transition. Hence clock recovery methods based on the detection of the transition of the clock transition are problematic, depending greatly on the quality of the received signal.
Another digital transmission clock recovery technique includes detecting the presence of a synchronization bit that is used to initial a data signal bit and detecting when the maximum intra-bit signaling distance has been exceeded. This method however, requires the addition of at least one synchronization bit, hence reducing data transmission throughput and increasing circuit complexity.
There is, therefore, a need in the industry for a system addressing these and other related and unrelated problems.
SUMMARY OF THE INVENTION
The present invention provides a system for adjusting the timing and phase angle of a recovered data clock signal from a received data signal includes a plurality of counters and a phase state machine. Each counter within the plurality of counters determines a number of samples having a logical one (1) value within a particular portion of a period of the received data signal. Each counter then compares the number to a predetermined threshold value. Each counter transmits a signal indicating whether the number of samples having a logical one (1) for each portion of received data signal's period is greater than, is less than, or is equal to the predetermined threshold. The phase state machine receives the signals transmitted by each counter and adjusts the phase angle of the recovered data clock signal based on the signals received from each counter.
According to the first preferred embodiment of the present invention, the first counter counts digitally sampled data samples within a center portion of the data period of the received data signal.
According to the first preferred embodiment of the present invention, the second counter counts digitally sampled data samples within a portion of the data period having samples detected prior to the center portion samples.
According to the first preferred embodiment of the present invention, the third counter counts digitally sampled data samples within a portion of the data period having samples detected after the center portion samples
According to the first preferred embodiment of the present invention, the effective counting windows of the second and the third counters can be slightly overlapped, around the expected location of the transmission clock transition, ensuring if one counter counts the transition, the other counter will also count the transition.
According to the second preferred embodiment of the present invention. the effective counting windows of the second and third counter are not overlapped.
Thus, the present invention provides a method for digitally detecting the transmission data clock edge transmission and to allow for adjustments to accurately track the transmission clock. The present invention provides a method for digitally detecting the transmission data clock edge which does not depend on the actual detection of the clock edge transition, which can be difficult to detect.
Objects features, and advantages of the present invention will become apparent upon reading and understanding the present specifications, when taken in conjunction with accompanying drawings.
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Chin Stephen
Liu Shuwang
Oki Telecom, Inc.
Thomas Kayden Horstemeyer & Risley LLP
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