System and method for adhesion improvement at an interface...

Details System and method for adhesion improvement at an interface... System and method for adhesion improvement at an interface...

2000-07-12

2003-11-04

Nguyen, Ha Tran (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S751000, C257S761000, C257S762000

Reexamination Certificate

active

06642619

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to the manufacture of microdevices, and, more particularly, to the manufacture of various structures within such microdevices.
BACKGROUND OF THE INVENTION
In the manufacture of microdevices and integrated circuits, various structures are formed on appropriate substrates using various techniques including deposition and photolithography. As is known in the art, there are a multitude of structures and/or electrical components that may be created, including transistors, pins, vias, etc., that make up circuits that perform the functionality of a particular integrated circuit and/or microdevice. There are many different chemical materials employed in the making of these structures and/or electrical components. For example, Copper may often be employed to provide electrically conductive pathways in a particular integrated circuit. Various materials may also be employed as insulators, etc.
Many different materials are used to create the various structures within integrated circuits depending upon their physical and electrical properties. In some cases, two particular materials used in the manufacture of an integrated circuit are kept separated by so called barriers to prevent unwanted reaction and diffusion. Two such materials that are so separated include Fluorine doped Silicon Oxide (SiO
2
) and Copper (Cu).
To explain further, a structure comprising Fluorine doped SiO
2
is often formed on an appropriate substrate in a Plasma Enhanced Chemical Vapor Deposition (PECVD) System by introducing Tetrafluoro-Silane (SiF
4
) and Tetraethylorthosilicate (C
8
H
20
Si) into the PECVD chamber in the presence of an appropriate radio-frequency (RF) signal or other precursors in a High Density PECVD system. The Fluorine doped SiO
2
structure may comprise, for example, a layer structure with vias that are etched where appropriate as is known in the art.
In the case where vias are etched into the Fluorine doped SiO
2
structure, the particular integrated circuit may include Copper pins that are formed within the vias to act as electrically conductive pathways using appropriate electroplated Copper metallization techniques. Unfortunately, when Copper comes into direct contact with Fluorine doped Silicon Oxide, the Copper molecules tend to enter into the Fluorine doped Silicon Oxide by way of diffusion, thereby resulting in undesirable alteration of the properties of the Fluorine doped Silicon Oxide.
To prevent such diffusion, a barrier layer of Tantalum (Ta) may be placed between the Fluorine doped Silicon Oxide structure and the Copper (Cu) to act as a Copper barrier to prevent such diffusion. Unfortunately, conventional interfaces between Fluorine doped Silicon Oxide structures and Tantalum barrier layers lack structural integrity. Specifically, the Fluorine retained in the Silicon Oxide tends to retain moisture that negatively affects the adhesion between the Tantalum barrier and the Fluorine doped Silicon Oxide. Consequently, the structural integrity of integrated circuits that include such an interface is compromised.
SUMMARY OF THE INVENTION
In light of the forgoing, the present invention provides a Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface and method for manufacturing the same that ensure the structural integrity of integrated circuits that include a Fluorine doped Silicon Oxide structure and a corresponding Tantalum barrier layer. Accordingly, the Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface comprises an amount of Silicon Nitride (SiN) in a surface region of a Fluorine doped Silicon Oxide structure. The concentration of Fluorine in the surface region is depleted with respect to a concentration of Fluorine in the remaining portion(s) of the Fluorine doped Silicon Oxide structure. The Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface also includes an amount of Tantalum Nitride (TaN) in the surface region. Finally, a Tantalum barrier layer is deposited over the surface region.
The present invention can also be viewed as providing a method for manufacturing Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface. In this regard, the method can be broadly summarized by the following steps: treating a surface region of a Fluorine doped Silicon Oxide structure to allow an amount of Tantalum (Ta) to adhere thereto, and, depositing an amount of Tantalum (Ta) over the surface region.
The Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface of the present invention provides distinct advantages. For example, by virtue of the existence of the Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface, there is greater adherence between the Tantalum barrier layer and the Fluorine doped Silicon Oxide structure that ultimately results in greater structural integrity in the resulting integrated circuit. Also, the Silicon Nitride within the Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface provides a Fluorine barrier to prevent the migration of Fluorine therethrough. Additionally, the underlying manufacturing steps taken to generate the Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface may be performed in-situ with preceding manufacturing steps taken to create an integrated circuit structure. Consequently, existing manufacturing facilities may be employed during the manufacture of the Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface, thereby reducing cost. Also, the steps taken during the manufacture of the Fluorine doped Silicon Oxide (SiO
2
)/Tantalum interface are easily integrated into conventional manufacturing procedures.


REFERENCES:
patent: 6177364 (2001-01-01), Huang

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