Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-08-16
2003-05-20
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C713S401000, C711S141000
Reexamination Certificate
active
06567885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to cache synchronization, and more particularly to address broadcast synchronization to a plurality of potentially responding devices.
2. Description of the Relevant Art
Maintaining cache coherency in an N-way system, where N is the number of processors in the system, is essential. In a system where N is small (N<4), the address buses of all cacheable devices may be physically connected together. Therefore, all cacheable devices may see a cache miss address simultaneously. On the other hand, when a system of N is large (N>4), it becomes electrically unfeasible to connect the address buses of all cacheable devices together.
One approach for achieving cache coherency in a system with large N, is by broadcasting the cache miss addresses to all cacheable devices simultaneously, through an address broadcast network. The address broadcast network has an address-in and an address-out connection to each of the cacheable devices. When a device sends a cache miss address to the address broadcast network, the address gets buffered, and then broadcast to all devices concurrently, so that all devices may check or update their tags appropriately.
One problem with building an address network in hardware for large systems (N>4) is that one needs a very large pin count ASIC (Application Specific Integrated Circuit) to accommodate all address-ins and address-outs for all cacheable devices to maintain address synchronization. The expense of building a large pin count ASIC to accommodate all address-ins and all address-outs for all cacheable devices limits this solution to only a very small number of computer systems.
Another possible solution is to slice the address network into X (X>1) slices for a small ASIC solution. The problem with address slicing is that using typical request and grant flow control techniques between address slices to maintain address synchronization requires a computer system performance degradation that is unacceptable.
What is needed is a mechanism for achieving synchronization between address network slices without substantial performance degradation. The request and grant flow control technique used should require a minimum number of control signals passing between each switch.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a system and method providing address broadcast synchronization using multiple switches. Each switch may be an application specific integration circuit (ASIC) or a separate switching device. By dividing address requests between more than one switch, addresses may be broadcast concurrently to a plurality of devices, which may advantageously provide for a higher system performance at a lower cost.
In one embodiment, the system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch. The second switch selects a selected address request, and the first and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request.
A method is also contemplated, in one embodiment, for concurrently providing addresses to a plurality of devices. In one embodiment, the method comprises receiving at a first switch a first address and a corresponding first request from a first device. The method receives at a second switch a second address and a corresponding second request from a second device, with the first switch being different from the second switch. The method transfers the second address and the corresponding second request to the first switch. The method delays the corresponding first request in the first switch. The method arbitrates in the first switch between the corresponding first request and the corresponding second request but rather the first address or the second address will comprise a first transmission. The method concurrently broadcasts to a plurality of devices the first transmission from the first switch and the first transmission from the second switch where the first transmission from the first switch and the first transmission from the second switch are identical.
In another embodiment, a system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch comprises a broadcast buffer, an incoming buffer, a delay circuit, and a broadcast arbiter. The broadcast buffer is coupled to receive addresses of the address requests from the second plurality of sources. The incoming buffer is coupled to receive addresses of the output of the address requests from the first plurality of sources from the first switch. The delay circuit is coupled to receive the address requests from the second plurality of sources. The delay circuit is configured to delay the address requests from the second plurality of sources for a predetermined length of time. The broadcast arbiter is coupled to arbitrate between ones of the address request from the second plurality of sources and ones of the output of the address request from the first plurality of sources from the first switch for a selected address request. The first switch and the second switch are further configured to broadcast concurrently a corresponding address to the selected address request selected in the broadcast arbiter.
In still another embodiment, a method of arbitrating in a first switch and a second switch between requests to the first switch and the second switch is disclosed. The method comprises tracking which switch was most recently selected and tracking which switch is next to be selected. In response to a reset, the method selects the first switch and indicates that the second switch is next to be selected. In response to only a local request to the first switch or only a remote request to the second switch, the method selects the first switch and indicates that the first switch is next to be selected. In response to only a local request to the second switch or only a remote request to the first switch, the method selects the second switch and indicates that the second switch is next to be selected. In response to both a local request and a remote request concurrently, the method selects the switch which was not most recently selected, and the method indicates that the switch not most recently selected will be the next to be selected. Otherwise, the method selects the first switch and indicates the switch most recently selected as the next to be selected.
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Jacunski et al., “All-to-all broadcast on switch-based clusters of workstations,” Oct. 1998, pp. 1-18.
International Search Report for application No. PCT/US 00/22563, mailed Mar. 6, 2001.
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