Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2005-07-05
2005-07-05
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000, C711S167000, C711S170000, C365S189011, C365S194000
Reexamination Certificate
active
06915443
ABSTRACT:
The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.
REFERENCES:
patent: 6253333 (2001-06-01), Bogumil et al.
patent: 6370200 (2002-04-01), Takahashi
patent: 6496911 (2002-12-01), Dixon et al.
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Neil H. E. Weste and Kamran Eshraghian, “Principles of CMOS VLSI Design”, Addison-Wesley Publishing Company, Second Edition, pp.: 17-18.
Brownell Paul V.
McBride Christopher D.
McJunkin Timothy R.
Browne Lynne H.
Trujillo James K.
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