Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1999-07-30
2001-03-13
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S157000, C710S066000, C710S120000
Reexamination Certificate
active
06202120
ABSTRACT:
I. FIELD OF THE INVENTION
The present invention relates to the main system memory in a microcomputer system, and more particularly, to a novel system memory architecture and method for allowing data access at high speeds in a burst mode.
II. RELATED ART
Computer systems have traditionally been classified into three groups in the following order in terms of size: mainframe computers, minicomputers, and microcomputers. Size in this context refers to memory size and the number of users as well as the associated management sophistication. Moreover, computer designers of the different computer sizes have varying design priorities, relating to complexity, speed, quantity of data, cost, and the consumer.
Until the invention at hand, a burst mode data transfer from the system memory directly to the central processing unit was considered a sophisticated computer concept for high end computers. Utilization of this concept was limited to computers on the larger and expensive end of the computer spectrum, namely mainframes and minicomputers, which require processing of large quantities of data at high speeds. However, burst mode data transfers could be found internally to microprocessor chip architectures in relation to an internal cache. Thus, although mainframe, minicomputer, and microchip designers were predisposed with the concept of burst mode, microcomputer designers were not so predisposed because of the lack of a need.
As the microcomputer industry evolved, it has become necessary to achieve greater processing speeds in microcomputers which have been progressively used more for compute-intensive applications. These applications include, for example, high resolution graphics displays, high performance computer automated design (CAD) workstations, high speed local area networks (LAN), and recently the new Extended Industry Standard Architecture (EISA) peripherals which are being developed to handle 32-bit burst data transfers at up to 33 megabytes per second. As a result, microcomputer designers, who deal regularly with interfacing discrete computer components are seeking ways to increase the speed of component interaction. It has been realized that most of the microcomputer system's time is utilized during computation or during the movement of data between the system memory and the central processing unit.
Aware of the needs of the rapidly expanding microcomputer industry, microchip designers have designed and developed a microprocessor which can operate on data externally in a burst mode. This microprocessor is the Intel 80486 microprocessor (manufactured by Intel Corporation, California, USA) having an internal 8 Kilobyte internal cache. The Intel 80486 microprocessor was developed to improve the Intel 80386 microprocessor design and to operate externally in a burst mode.
i
486
Microprocessor,
Intel Corporation, April 1989, Order Number 240440-001, which is incorporated herein by reference.
Using conventional system memory comprised generally of DRAMs in conjunction with the Intel microprocessors has not fully exploited the microprocessor speed capabilities because of the limited speed of such memories. To maximize the data exchange rate between system memory and the microprocessor, microcomputer designers have been quick to interface external caches with the central processing units to more readily transport system memory data to the central processing unit. Several 80486 machines have been announced by Apricot and Advanced Logic Research having an Intel 80486 microprocessor which is used in conjunction with an external cache.
However, addition of an external cache to the Intel 80486 microprocessor to improve speed has disadvantages. Acquiring data from an external cache is more time consuming than acquiring it from the internal cache of the 80486. An external cache needs to be situated physically near the 80486 microprocessor. The external cache takes up valuable, limited real estate in the microcomputer. Moreover, the external cache represents an additional cost.
Until the present invention disclosed below, no microcomputer system memory in the marketplace or elsewhere has been capable of transferring data in a burst mode directly to the microprocessor without the need for an external cache in order to achieve high processing speeds at a consumer affordable cost. In this regard, see N. Baran, “EISA Arrives,”
Byte Magazine,
v. 14, number 12, November 1989 (cover story), which is incorporated herein by reference.
SUMMARY OF THE INVENTION
Representing a substantial effort on the part of several microcomputer designers and engineers over a span of a year, the present invention overcomes the previously mentioned problems and deficiencies in the prior art related to high speed data transfers in a burst mode from system memory directly to the Intel 80486 microprocessor, where no external cache is used.
The present invention comprises a system memory architecture having at least two parallel 64-bit memory buses in electrical communication with a 32-bit host bus. Each 64-bit bus may be connected to a series of single in-line memory (SIMM) modules having dynamic random access memory (DRAM) banks. Moreover, 32-bit bidirectional latching transceivers for each 64-bit bus may be used to transmit data from each 64-bit memory bus to the 32-bit host bus. This memory architecture of the present invention helps to provide fast data acquisition by minimizing the propagation delays caused by the capacitance loading of the SIMMs. More specifically, the 32-bit transceivers can drive a heavier host bus load better than the DRAMs can drive a heavier SIMM memory bus load. The memory architecture of the present invention further permits retrieval of two dwords of data upon each DRAM access, thereby cutting in half the number of necessary DRAM accesses which are relatively slow. Consequently, the memory data speed can approach the speed at which the microprocessor functions.
Another embodiment of the present invention has a host bus connecting the system memory comprised of DRAMs with an Intel 80486 microprocessor. Such compatibility with a conventional microprocessor allows for easy integration into microcomputer architectures. Notwithstanding the use of DRAMs, which are relatively slow compared to cache memories, the system memory achieves extremely fast, data transmission speeds to the Intel 80486 microprocessor.
Yet another embodiment of the present invention is a method of high speed data retrieval from system memory in a microcomputer. The system memory has at least two 64-bit system memory buses connected in parallel to a 32-bit host bus. The method of the present invention involves the steps of selecting one of the 64-bit system memory buses, retrieving 64 data bits from the 64-bit system memory bus, transmitting a first set of 32 data bits of the 64 data bits onto the 32-bit host bus, and transmitting a second set of 32 data bits of the 64 data bits onto said 32-bit host bus. The method permits simultaneously retrieval of two 32-bit dwords and further provides a procedure for transferring 64 data bits onto a 32-bit host bus. Moreover, the latter three steps of the method can be repeated to thereby retrieve 4 dwords in a burst mode from the same 64-bit system memory bus.
Further objects and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that any additional objects and advantages be incorporated herein.
REFERENCES:
patent: 4467447 (1984-08-01), Takahashi et al.
patent: 4489395 (1984-12-01), Sato
patent: 4866603 (1989-09-01), Chiba
patent: 5307469 (1994-04-01), Mann
patent: 5960450 (1999-09-01), Lang et al.
Bassett Carol Elise
Begur Sridhar
Campbell Robert
Lang Marilyn Jean
Ellis Richard L.
Hewlett--Packard Company
LandOfFree
System and method for accessing data between a host bus and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for accessing data between a host bus and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for accessing data between a host bus and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2461794