Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate
2001-09-06
2003-07-15
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
Reexamination Certificate
active
06594184
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a memory array system, and more particularly to a memory array system which permits the accidental simultaneous assertion of a plurality of word addresses without corrupting data stored in the array or otherwise damaging the array.
BACKGROUND OF THE INVENTION
Memory arrays include cells that share data lines for storing digital information to and retrieve digital information from the cells. Each memory cell stores the smallest unit of digital information, known as a “bit”. Typically, a predetermined number of bits, such as eight, cooperate to form a larger type of digital information known as a “word”. A unique word address is associated with each group of cells that cooperate to store a word of digital information. When a word address is enabled or asserted, digital data can be either stored or retrieved from the group of cells at the word address. During an instruction cycle of a read operation, only a single word address is enabled from among a plurality of word addresses sharing data lines in order to protect the integrity of the data on the shared data lines.
FIG. 1
, for example, is a highly schematic illustration of a conventional dual-ended memory array
10
for storing digital information at cells X
1
through X
N
, where there are N cells in the array. Each cell stores a bit of digital information that is either a predetermined low voltage value (logic “0”) or a predetermined high voltage value (logic “1”). For simplicity of illustration, a word comprises a single bit of digital information stored in a single cell associated with the word address, but typically a word includes a plurality of bits of digital information stored in a plurality of cells associated with the word address. Each cell includes cross coupled inverters
14
a
and
14
b
associated with a unique word address that is enabled via one of the word lines WL
1
through WL
N
. If a word or address line is enabled during a read operation, pass transistors
16
a
and
16
b
associated with the cell at the enabled word address are turned on to pass the bit of digital information stored in the cell onto the data or bit line BL, as well as the digitally inverted or complemented value of the bit of information onto the inverted data or bit line BL-INV.
A sense amplifier
18
is coupled between the bit lines BL and BL-INV to measure the difference in voltage therebetween. The voltage between the bit lines BL and BL-INV when only one word address is enabled is different from that when two word addresses are accidentally simultaneously enabled due to a defective operation of a conventional address decoder (not shown). The sense amplifier
18
detects when a defective read operation has occurred and consequently when the retrieved data should be ignored. The data should be ignored because the simultaneous enabling of more than one word address can cause the data stored within the cells to be corrupted. Another drawback with simultaneous enablement of two word addresses is that the memory array can become unstable because cells associated with different word addresses sharing the same bit lines can “fight” one another by simultaneously attempting to pull a bit line up to logic “1” and down to logic “0”. This unstable condition can cause the memory array to draw excessive current that results in permanent damage to the memory array.
SUMMARY OF THE INVENTION
An electronic memory system includes a memory array including a plurality of memory cells each storing a bit of digital information. Each memory cell is from among a group of cells associated with a word address and communicates with a read enable line for activating the group of cells associated with the word address for data retrieval during a read operation. Further, each cell communicates with at least one data output line shared by other cells from among other word addresses for data retrieval from the group of cells associated with the enabled word address during a read operation. Bits of digital information retrieved from cells sharing the same data output line during a read operation are logically OR-ed together in order to prevent damage to the memory array or corruption of data stored therein should enablement signals accidentally be sent simultaneously to a plurality of word addresses. Preferably, the system includes dynamic logic to perform the logical OR operation.
In addition, a method is provided for accessing a memory array with a plurality of memory cells each storing a bit of digital information. Each memory cell is from among a group of cells associated with a word address and communicates with a read enable line for activating the group of cells associated with the word address for data retrieval during a read operation. Each cell communicates with at least one data output line shared by other cells from among other word addresses for data retrieval from the group of cells associated with the enabled word address during a read operation. A read enable is asserted during a read operation for retrieving data from a group of cells associated with the enable word address. Bits of digital information retrieved from cells sharing the same data output line during a read operation are logically OR-ed together in order to prevent damage to the memory array or corruption of data stored therein should enablement signals accidentally be sent simultaneously to a plurality of word addresses. Preferably, the system includes dynamic logic for the logical OR function.
The memory array system permits the accidental simultaneous enablement of more than one word address during a read operation without corrupting data stored therein or drawing excessive current which might damage the memory array.
REFERENCES:
patent: 5398206 (1995-03-01), Akizawa et al.
patent: 5477484 (1995-12-01), Nakashima
patent: 5880990 (1999-03-01), Miura
patent: 5940332 (1999-08-01), Artieri
patent: 6286116 (2001-09-01), Bhavsar
Eisenberg Jason
Knapp Micah C.
Lamere Marc E.
Staraitis Julie M.
McCormick Paulding & Huber LLP
Sun Microsystems Inc.
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