Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-01-29
2008-01-29
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S005110, C714S042000, C714S720000, C714S723000, C365S201000
Reexamination Certificate
active
07325176
ABSTRACT:
Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instance, memory test iterations in one Mbyte portions using 128-bit SIMD registers, 64-bit MMX registers, ADD and SUB instructions, the MOVNTDQ instruction, and relying on an initial setting of the gate A20and protected mode result in a substantially accelerated memory test.
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Dennis Lowell B.
Larson Mark A.
Dell Products L.P.
Hamilton & Terrile LLP
Holland Robert W.
Trimmings John P
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