Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-13
2002-11-26
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06487701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuit chips, and more particularly to a system and automated methodology for ac performance tuning of tubbed semiconductor ASIC chips in a timing-safe environment by repairing detected AC defects in the semiconductor die.
2. Description of Related Art
As the performance targets for integrated circuits increase, the presence of AC defects within the manufactured device is of greater concern due to test cost and yield impacts. While present test methodologies test for AC defects, products failing these tests are discarded or sorted into less-profitable speed bins.
In order to improve the AC yield characteristics produced by IC devices, a system and method for tailoring device performance post-manufacture is disclosed. The means described allows for tailoring of the bulk voltage supplied to various well structures within the die, thereby altering the effective threshold voltage and AC performance of the devices present within the well, thus in effect, repairing detected AC defects.
The value of the threshold voltage of a transistor, V
T
, particularly a MOS transistor, is determined in part by the fabrication process specifications, i.e., the channel length, channel width, doping, and the like. Thus, it is possible to set V
T
to a desired (predetermined) level during fabrication. It is difficult, however, to choose the VT such that the transistor will operate efficiently over a wide range of supply voltages. Additionally, manufacturing inconsistencies will also cause variations in the threshold voltage among individual transistors.
Several innovative techniques for controlling well bias have been previously disclosed, however, all lack a defined methodology for performing in-situ testing of semiconductors. Moreover, these prior art techniques have not been built around characterized technology circuit delay timing rules, which allow for safe tailoring of threshold voltages via well bias in order to speed up AC performance without introducing new timing problems such as undesired fast paths.
The bulk of today's semiconductor integrated circuits are designed using Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs). Although in most designs, MOSFETs are treated as three-terminal devices where the conductivity between the source and the drain of the device is controlled by a gate voltage, MOSFETs are inherently four-terminal devices, in which a fourth terminal, the bulk node, affects the parametric characteristics of the device. The threshold voltage for a MOSFET, V
T
, is the gate voltage at which conduction between the source and drain begins. This threshold voltage may be tailored by adjusting the bulk voltage, thereby altering the electric field impressed upon the MOSFET during normal operation. Early MOSFET products used p-FETs or n-FETs having differentiation between load and switching devices. These junctions were typically provided by implant tailoring during manufacture. All devices within the die shared a common bulk node with a voltage supplied coincident with the power supplies for the die. In later CMOS devices in which both n-FETs and p-FETs were integrated within the same die, tubs or wells of bulk material were used to house either the n-FET or p-FET. The bulk connections in these devices were generally tied to one of the voltage rails, or alternatively, for devices within a well or tub only, to a node within the operative circuit. Although in many cases, the base wafer upon which the FETs without tubs were produced was highly resistive, the isolation between FET regions was not sufficient for independent back biasing of device regions without wells. In each case, a voltage potential was provided which could not be altered in reference to the supply rails for the die.
In more advanced CMOS technologies, local isolation of both n-FETs and p-FETs within tubs has been achieved by the stacking of tub structures. As an example, n-FET devices fabricated on a p-type wafer may be isolated by first implanting an n-well within the wafer and subsequently creating a p-well within the larger n-well. In these cases, care is taken to bias the intervening tub appropriately to prevent semiconductor latch-up.
In silicon-on-insulator (SOI) technology, n-FETs and p-FETs are both isolated in the locale of device level tubs; however, shallow SOI technologies leave the body of the device floating.
Typical methods for adjusting threshold voltages in semiconductors include disconnecting each bulk region or well from its associated fixed rail voltage and alternatively making a connection to a set of devices acting as a potentiometer to adjust the bias voltage of the bulk region or well, independent of the fixed rail voltages. Each well can be connected to a dedicated potentiometer, or share a potentiometer with other wells on the die. Several embodiments of the bulk bias potentiometer have been realized.
In
FIG. 1
, the bulk connection
12
is made at the connection point between two series resistors R
1
, R
2
bridging the V
CC
5
to V
SS
10
envelope. The resistors R
1
and R
2
are of an arbitrary size which considers power dissipation, accuracy, and predicted optimum bias voltage settings for the circuit, and are trimmable via laser or other types of fuse blow. AC testing is typically performed with nominal biasing of the stack. If a fail occurs, the voltage applied to the stack, V
CC
5
, is assumed separate from the main V
SS
supply
10
of the chip, and may be moved higher or lower. The test is repeated to determine a setting at which the AC test produces adequate yields. The empirically determined V
CC
value
5
is used with either the expected nominal values of the resistors, or the expected ratio of resistor R
1
and resistor R
2
coupled with an empirical resistor value. This is calculated by measuring the ground current of the stack at a known V
CC
to determine the bulk bias voltage needed for yield (the bias tap supplies a tub with back biased diodes which generally has very small leakage currents). The calculated voltage is then converted to a trim percentage necessary at either resistor R
1
or resistor R
2
to obtain the desired bias voltage given the operational V
CC
value for the silicon. Additional capability can be added by placing shunt devices in parallel with one or more of the resistors in the stack (R
1
and R
2
may consist of several segments) such that the well may be biased at the V
CC
rail. This capability also adds additional accuracy to resistor measurements which precede device trim calculations. The trimming accuracy and achievement of the desired AC effect is determined by measurement of V
SS
current at the specified voltage and by the AC test post trim.
Another method for adjusting threshold voltages in semiconductors is depicted in FIG.
2
. This method involves removing the direct connection to V
SS
for the stack at the chip's edge
14
in favor of a supply voltage via a bandgap reference system
20
. The reference system includes the generation of a V
CC
5
, a temperature independent reference voltage, and a voltage reference multiplier
18
which may be adjustable. The bandgap itself provides for reference equivalence between the test and functional environments with the voltage multiplier, allowing for biasing of well voltages V
sub
above voltages normally possible with a bandgap device. If a voltage multiplication is adjustable, this function takes the place of V
CC
shifting during test. In cases where variable multiplication is not provided, the V
SS
reference, being separate from common ground, is assumed to be isolated from other grounds on the die, and can be moved to simulate V
CC
shifting.
In U.S. Pat. No. 5,917,365 issued to Houston, entitled “OPTIMIZING THE OPERATING CHARACTERISTICS OF A CMOS INTEGRATED CIRCUIT,” an n-channel transistor and a p-channel transistor each have a voltage bias applied to a common substrate. A control circuit is operated to apply the varying voltage bias to the common substrate in
Dean Alvar A.
Hayes Jerry D.
Iadanza Joseph A.
Keller Emory D.
Ventrone Sebastian T.
Curcio Robert
DeLio & Peterson LLC
Siek Vuthe
Walsh Robert A.
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