Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2006-01-10
2006-01-10
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S500000, C370S538000
Reexamination Certificate
active
06986073
ABSTRACT:
A communications system operates with an internal pipeline clock rate that is higher than that of any port used in the system. In an xDSL environment, this rate is higher than a DMT symbol rate used in the channel. In this manner, communications for the various ports can be synchronized and pipelined for transmit/receive operations. In addition, the higher rate results in idle processing periods, during which stuffing symbols are generate to maintain synchronism and/or pass along control information. The internal pipeline clock rate is selected to be higher than rate that may be encountered as well during an initialization routine and normal transmissions. The pipeline clock is also programmable so as to permit power management of the system.
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Brian R. Wiese and Ja
Hsu Winston
Lee Thomas
Realtek Semiconductor Corp.
Suryawanshi Suresh
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