Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-04-04
2006-04-04
Chace, Christian P. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07024520
ABSTRACT:
A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing the address of the block at that line, and its state. A duplicate copy of the tag information (DTAG) for each processor cache is also provided, and each section of the DTAG that corresponds to a given processor is organized into a primary DTAG region and a secondary DTAG region. The secondary DTAG region preferably stores tag information for a dirty version of a block, while the write back of the block is in flight to memory. This frees the primary DTAG region to store tag information for a block other than the dirty block, but using the same cache line.
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Tierney Gregory E.
Van Doren Stephen R.
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