Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-07-02
2009-06-23
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C365S201000
Reexamination Certificate
active
07552413
ABSTRACT:
A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
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Agarwal Vikas
Lee Michael Ju Hyeok
Shephard, III Philip G.
Garbowski Leigh Marie
Gerhardt Diana R.
Harris Andrew M.
Harris, Atty at Law, LLC Mitch
International Business Machines - Corporation
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