System and apparatus for partially flushing cache memory

Details System and apparatus for partially flushing cache memory System and apparatus for partially flushing cache memory

1995-12-19

1998-07-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711115, G06F 1212

Patent

active

057784310

ABSTRACT:
A computer system is disclosed for selectively invalidating the contents of cache memory in response to the removal, modification, or disabling of system resources, such as for example, an external memory device. The computer system includes an interface unit which defines an address window for the particular system resource. The address window is implemented through the use of a lower address register and an upper address register, which are loaded in response to a lower and upper enable address signal. An upper comparator compares each tag address with the upper address register value, and a lower comparator compares each tag address with the lower address register value. If the tag address falls within the window, it is flushed by the generation of appropriate control signal. In an alternative embodiment, the present invention can be implemented through software by instructions in microcode. As yet another alternative, the present invention can be implemented by comparing each memory window address value with the stored tag address in the cache.

REFERENCES:
patent: 4471429 (1984-09-01), Porter et al.
patent: 4713755 (1987-12-01), Worley, Jr. et al.
patent: 4766534 (1988-08-01), DeBenedictis
patent: 4847804 (1989-07-01), Shaffer et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5195089 (1993-03-01), Sindhu et al.
patent: 5197144 (1993-03-01), Edenfield et al.
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5325504 (1994-06-01), Tipley et al.
patent: 5353423 (1994-10-01), Hamid et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5359723 (1994-10-01), Mathews et al.
patent: 5363496 (1994-11-01), Kato et al.
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5428761 (1995-06-01), Herlihy et al.
patent: 5551006 (1996-08-01), Kulkarni
Patent Abstracts of Japan, vol. 018, No. 353 (P-1764), Jul. 4, 1994 & JP,A,06 089229 (PFU LTD), Mar. 29, 1994.
Jim Handy, "The Cache Memory Book--Existing Copy-Back Coherency Protocols," Academic Press, Inc., San Diego California, 1993, pp. 158-190.
Robin Edenfield, Bill Ledbetter, Jr., Ralph McGarity, "The 68040 On-Chip Memory Subsystem," The Institute of Electrical and Electronics Engineers, Inc., Feb. 1990, Computer Society International Conference (COMPCON), Spring Meeting, Los Alamitos, No. Conf. 25, pp. 264-269.
Mark Atkins, "Performance and the i860 Microprocessor," IEEE Micro, (Oct. 1, 1991). vol. 11, No. 5, pp. 24-27, 72-78.

Affiliated with

Also associated with

Rating

System and apparatus for partially flushing cache memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and apparatus for partially flushing cache memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and apparatus for partially flushing cache memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1218597