Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-07-07
2001-07-31
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C713S002000
Reexamination Certificate
active
06269455
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system for, and a method of, processing information about the locations of defective memory cells. In particular, the invention relates to a system for, and a method of, storing the locations of defective memory cells received from a memory test system so that the size of the memory required for storing the locations is reduced.
BACKGROUND OF THE INVENTION
In the memory manufacturing industry, memory cells on a memory device (such as a semiconductor memory) are tested after fabrication of the device.
Conventionally, memory devices have a main memory comprising a large number of memory cells, and also a small number of redundant memory cell structures which can be substituted for any defective memory cells in the main memory. During the test process, the location of defective cells in the main memory is identified in order that through a process of redundancy allocation, these redundant memory cell structures can be configured to replace the defective cells in the main memory.
Other applications of memory test include the examination of electrical or functional parameters of the memory for engineering or quality control purposes, or verification of the operation of the memory.
Test systems used for testing memory devices must be able to test each new generation of memory devices at the maximum speed of the new device. The test systems must also be able to record a large number of locations. These factors combine to create a requirement for a large and expensive memory (called the fault capture memory or error catch RAM) in test systems because the fault capture memory must be the same size and operate at the same speed as the memory device under test. Some systems have used FIFOs to reduce the amount of RAM, but this still requires a large memory in the control system to which the tester is connected to process or view the defect data.
When the latest generation of memory devices is manufactured, there must be a test system available which is capable of testing these new memory devices; however, these test systems must be fabricated using the previous generation of memory devices. To enable the test systems to operate effectively, the requirement for storing the locations of defective cells is met by emulating the fault generating capacity of the new memory devices to be tested using arrays of smaller (previous generation) memory devices having the fastest timing characteristics available for those (previous generation) devices.
For example, a test system having 256 pins, testing sixteen 256 Mbit capacity memory devices, each device being organised as 16 M×16 bits, will require 4 Gbits (256 pins×16 Mb) of high speed fault capture memory to obtain single bit resolution, or if the 2 least significant address bits are ignored to obtain a 4×4 cell resolution, 1 Gbit of high speed memory. A 1024 pin tester would require 4 Gbit of high speed fault capture memory at the same defect resolution (a 4×4 cell) but this would test sixty-four 256 Mbit capacity memory devices.
This high speed fault capture memory (also called defect store memory) normally comprises Static Random Access Memory (SRAM) and can cost 30% of the total hardware cost of the test system. It is therefore highly desirable to be able to reduce the amount of fault capture memory required.
One proposed solution, which is used in some test systems, is to maintain a list of defects rather than a full map (which would indicate for each cell whether that cell is working or defective). However, this list overflows when the test system is testing a number of memory devices concurrently and one or more of those memory devices contains a large number of defects. When the list overflows, either the test sequence must be interrupted or some defect data must be discarded. Also, the controller to which the tester is attached still requires a large amount of memory, and the transfer of the data to the controller is slow.
Another prior art solution is to capture a 1:1 bitmap from the tester, requiring a large amount of storage in the tester and in a computer to which it is linked, and then to apply digital signal processing techniques to filter the data. This produces a system with negative losses, that is, it loses some of the original data, limiting its application. Even with a communication channel between the tester and computer operating at very high speed, this solution is slow because of the volume of data involved.
SUMMARY OF THE INVENTION
It is an object of the present invention to obviate or mitigate at least one of the disadvantages of the aforementioned systems.
This is achieved by using a compression means with defined zero to positive loss characteristics on data restoration to act on the defect data to create a representation of the fail bit map data which is a compressed form of the original data. This allows the lossless restoration of the original data, or a lossy reconstruction of the original data where additional defects may be apparent, as required by the application and the exact implementation chosen for the compression means.
This reduces the size of or obviates the fault capture memory in the memory test system, either in the tester or in the controller or workstation or both. This provides the principal advantages of reduced test hardware cost, faster test result downloads, support of fast browsing capabilities in workstations or computers accessing the compressed defect data, and fast selective retrieval from databases employing the compressed defect data.
The compression can be effective by using the fact that defective memory cells are distributed preponderantly along rows and columns in a memory device. Thus, where a fault occurs in one cell of a row or column, there is a much higher probability of there being another fault manifest as a dysfunction in another cell in the same row or column. The data compression means of many of the preferred embodiments uses this phenomenon to record the row or column that is defective, and optionally the tile, along with a compressed form of the locations affected.
Various statements of invention corresponding to the subject matter in the independent claims and the dependent claims, based on the entire disclosure of the specification are incorporated herein by reference.
REFERENCES:
patent: 4628509 (1986-12-01), Kawaguchi
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5317573 (1994-05-01), Bula et al.
patent: 5754556 (1998-05-01), Ramseyer
patent: 6026505 (2000-02-01), Hedberg
Hansen, Peter “Testing Conventional Logic and Memory Clusters Using Boundry Scan Devices as Virtual ATE Channels” 1989 International Test Conference, IEEE, Paper 7.1, p. 166-173.*
International Search Report.
Acuid Corporation Limited
Beausoleil Robert
Bonzo Bryce
Sughrue Mion Zinn Macpeak & Seas, PLLC
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