Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-13
2004-03-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06711730
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to integrated circuit package design and, more particularly, to synthesizing information about signal nets from multiple integrated circuit package models.
2. Related Art
Integrated circuits (ICs) are becoming increasingly large and complex, typically including millions of individual circuit elements such as transistors and logic gates. As a result of this increased size and complexity, IC designers are increasingly using electronic design automation (EDA) software tools to assist with IC design. Such tools help to manage the complexity of the design task in a variety of ways, such as by allowing ICs to be designed hierarchically, thereby enabling the design to be divided into modules and enabling the design task to be divided among multiple designers in a manner that limits the complexity faced by any one designer.
Various hardware description languages (HDLs) have been developed which allow circuit designs to be described at various levels of abstraction. A description of a circuit according to an HDL (referred to herein as an “HDL model” of the circuit) may, for example, describe a particular circuit design in terms of the layout of its transistors and interconnects on an IC, or in terms of the logic gates in a digital system. Descriptions of a circuit at different levels of abstraction may be used for different purposes at various stages in the design process. HDL models may be used for testing circuits and circuit designs, as well as for fabricating the circuits themselves. The two most widely-used HDLs are Verilog and VHDL (Very High Speed Integrated Circuits (VHSIC) Hardware Description Language), both of which have been adopted as standards by the Institute of Electrical and Electronics Engineers (IEEE). VHDL became IEEE Standard 1076 in 1987 and Verilog became IEEE Standard 1364 in 1995.
EDA tools are typically capable of converting a functional HDL description of a circuit design into a specific circuit implementation. The specific circuit implementation may be represented by a “netlist,” which identifies both the elements of the circuit and the interconnections among them. In general, a netlist describes the circuit design in terms of nodes and edges. Each node represents a circuit element and each edge represents an interconnection between two circuit elements. Netlists may describe circuits at various levels of abstraction. A netlist may, for example, describe circuit elements in terms of specific structural components (such as resistors and transistors) or in terms of high-level “cells” that may be decomposed into specific structural components and/or other cells. A netlist may, for example, describe the connections between cells in terms of specific cell-to-cell pin connections.
EDA tools are typically capable of converting a netlist into a physical layout of the circuit. The layout process involves both “placement” (assigning specific coordinates in the circuit layout to each cell) and “routing” (wiring or connecting cells together). The layout produced thereby defines the specific dimensions and coordinates of the gates, interconnects, contacts, and other elements of the circuit. The layout may have multiple layers, corresponding to the layers of the circuit. The layout may be used to form a mask, which in turn may be provided to a foundry to fabricate the integrated circuit itself.
One stage in the process of IC design is package design, which refers to the design of substrates (packages) for interconnecting layers of the IC. An IC typically includes multiple packages interconnected in layers. Each package, in turn, may include multiple layers. Packages within a single IC may be composed of varying materials having varying electrical properties. Individual signal nets (also referred to herein simply as “nets”) in the IC may be distributed across multiple packages. A package design must ensure that signals in the IC have sufficient power and maintain sufficient signal integrity when passing from one layer of the IC to another. As used herein, the term “signal net” (or simply “net”) refers to a collection of conductors that are connected to form a complete circuit connecting at least one output to at least one input.
As with IC design more generally, various tools exist for automating aspects of IC package design. Such tools typically provide a graphical user interface through which package designers may visually design the IC package in three dimensions. One such tool is Advanced Package Designer (APD), available from Cadence Design Systems, Inc. of San Jose, Calif. APD is a software program which allows the package designer to model the physical, electrical, and thermal characteristics of the package substrate. An APD package design database may be provided to a foundry to be used directly as manufacturing input for fabrication of the designed package.
Referring to
FIG. 1
, relevant features of a conventional system
100
for designing IC packages are illustrated in block diagram form. A package design tool (not shown), such as APD, maintains a plurality of package models
102
a-n
, each of which contains information defining a particular package in an IC design. The package models
102
a-n
may include, for example, information specifying the name, location, and length of each signal trace in each layer of the package models
102
a-n
. Each of the package models
102
a-n
is typically stored in a distinct database file in a computer system.
Package design tools typically allow a package designer to access and modify only a single one of the package models
102
a-n
at a time. To modify a particular one of the package models
102
a-n
, the package designer must typically use the package design tool to open the database file corresponding to the package model to be modified. Upon opening one of the package models
102
a-n
, the package design tool may provide a graphical user interface which displays a two-dimensional or three-dimensional representation of the package model and which allows the package designer to modify the package model. Techniques for creating and modifying packages using such package design tools are well-known to those of ordinary skill in the art. To modify a different one of the package models
102
a-n
, the package designer must typically close the current package model and use the package design tool to open the other package model.
Package design tools are typically capable of generating various kinds of reports containing information about the package models
102
a-n
. One such report is a net length report, which contains information about the package-specific (intra-package) path length of each signal net within a particular one of the package models
102
a-n
. In other words, for each signal net within a particular package, the net length report indicates the length of that portion of the signal net which runs through the package. Such a report is therefore referred to herein as a “package-specific net length report.”
For example, as shown in
FIG. 1
, a net length report generator
104
(which may, for example, be part of the package design tool that was used to design the package models
102
a-n
) generates package-specific net length reports
108
a-n
, each of which contains the package-specific path lengths of signal nets within a corresponding one of the package models
102
a-n
. For example, package-specific net length report
108
a
contains the package-specific path lengths of signal nets within package model
102
a.
The package-specific net length reports
108
a-n
may include various kinds of information about the path lengths of signal nets in the package models
102
a-n
. In their simplest form, for example, each of the package-specific net length reports
108
a-n
may contain a list of the names of all of the signal nets in the corresponding package model and the path length of each such signal net within the corresponding package model. A more detailed report may include information not only about the path length of each signal net within a packag
Frank Mark D.
McHardy William Bryson
Moldauer Peter Shaw
Hewlett--Packard Development Company, L.P.
Siek Vuthe
Tat Binh
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