Synthesizing a pixel clock with extremely close channel spacing

Details Synthesizing a pixel clock with extremely close channel spacing Synthesizing a pixel clock with extremely close channel spacing

2006-03-14

2006-03-14

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000

Reexamination Certificate

active

07013403

ABSTRACT:
A graphic system may include a pixel synthesizing device that uses two or more phase-locked loops (PLL's) in tandem in order to achieve a better M/N ratio. The two PLL's connected in tandem have an effective M/N ratio of (M1*M2)/(N1*N2). The pixel synthesizing device is operable to synthesize free-running (non-genlocked, or sync-master) pixel clock frequencies using a much greater variety of M and N. As a result, greater precision in specification of the pixel clock frequency is achieved, yielding greater precision in a frame rate of a particular video format. As a result, the allowable channel spacing is greatly increased, and the graphic system can select from a wide range of ultradense spaced pixel clocks.

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