Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-20
2004-03-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06701496
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer aided design tools used for designing and verifying integrated circuits.
COPYRIGHT NOTICE/PERMISSION
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data as described below and in the drawings hereto: Copyright © Silicon Graphics, Incorporated, 2000. All Rights Reserved.
BACKGROUND OF THE INVENTION
Electrical engineers use computer aided design (CAD) tools to design integrated circuits. The integrated circuit design process includes constructing the integrated circuit design out of simple circuits (e.g., “standard cells”) that are electrically connected together using wire interconnects. The CAD tool stores the standard cells and connections between them in well-known databases called “netlists.” A chip manufacturing foundry uses the netlist as input to build the physical integrated circuit.
As part of the design process, the CAD tool “places” and “routes” design information within a netlist using placing and routing processes (also called placers and routers) that are typically software programs executed by the CAD tool. The placer determines the optimum location of each standard cell within the integrated circuit layout on the semiconductor surface. The placer optimizes the placement location to reduce the distance between standard cells that are electrically connected to each other by wire interconnects (e.g., input/output lines). This is done to both (1) minimize the semiconductor area consumed by the integrated circuit; and (2) minimize the lengths of wire interconnects to reduce net capacitance within the design. The router optimizes the routing of input/output lines between connected standard cells, so that areas of the integrated circuit layout do not become overly congested by input/output lines.
After the engineer has used the CAD tool to design the logic of the integrated circuit, the engineer would like to verify that the circuit design operates as intended prior to actually building the physical chip that embodies the logic design. To accomplish this verification, the engineer typically uses logic simulation and timing verification tools, which test the design and verify that the timing of operations will fit within a clock cycle. If the timing of an operation does not fit within a clock cycle, timing is said to have failed, and the engineer must redesign the logic.
Thus, the engineer must run a variety of independent logic design, testing, and timing verification programs and manually use the output of the testing and timing verification programs to redesign the logic. This manual process is time consuming and cumbersome. Thus, there is a need for an automatic process for connecting the various design, testing, and timing verification programs together and analyzing timing results and using those results to redesign the circuit logic.
SUMMARY OF THE INVENTION
The present invention provides solutions to the above-described shortcomings in conventional approaches, as well as other advantages apparent from the description below.
The present invention provides a method, system, and program product for designing and verifying an electronic circuit. In one aspect, a circuit logic design is translated into a netlist using a synthesis tool. The synthesis tool receives inputs of placing, routing, and timing information. Timing delays in the logic design are represented in the netlist using the placing and routing information. It is determined whether a timing goal has been reached based on the timing delays. When the timing goal has not been reached, changes to the placing, routing, and timing information are made, and the synthesis tool is re-executed using the changed information until the timing goal is reached.
REFERENCES:
patent: 4896272 (1990-01-01), Kurosawa
patent: 5521836 (1996-05-01), Hartong et al.
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 5555188 (1996-09-01), Chakradhar
patent: 5757658 (1998-05-01), Rodman et al.
patent: 5787268 (1998-07-01), Sugiyama et al.
patent: 5910898 (1999-06-01), Johannsen
patent: 6099580 (2000-08-01), Boyle et al.
patent: 6145117 (2000-11-01), Eng
patent: 6295636 (2001-09-01), Dupenloup
patent: 6324678 (2001-11-01), Dangelo et al.
Schwegman Lundberg Woessner & Kluth P.A.
Siek Vuthe
Silicon Graphics Inc.
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