Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-24
2007-07-24
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10728570
ABSTRACT:
A method for the synthesis of multi-level combinational circuits with cyclic topologies. The techniques, applicable in logic synthesis, and in particular in the structuring phase of logic synthesis, optimize a multi-level description, introducing feedback and potentially optimizing the network.
REFERENCES:
patent: 5515292 (1996-05-01), Roy et al.
patent: 6105139 (2000-08-01), Dey et al.
patent: 6430726 (2002-08-01), Nakamura
patent: 6591231 (2003-07-01), Kurshan et al.
International Search Report for International PCT Application PCT/US03/38622 dated May 4, 2004.
Robert Allen Short, “A Theory of Relations Between Sequential and Combinational Realizations of Switching Functions”, Feb. 1961, pp. 1-115.
William H. Kautz, “The Necessity of Closed Circuit Loops in Minimal Combinational Circuits”, IEEE Transactions on Computers, Feb. 1970, pp. 162-164.
David A. Huffman, “Combinational Circuits with Feedback”, pp. 27-55.
Ronald L. Rivest, “The Necessity of Feedback in Minimal Monotone Combinational Circuits”, IEEE Transactions on Compubers, Jun. 1977, pp. 606-607.
Leon Stok, “False Loops through Resource Sharing”, IEEE, 1992, pp. 345-348.
Sharad Malik, “Analysis of Cyclic Combinational Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 7, Jul. 1994, pp. 950-995.
Anand Raghunathan et al., “Test Generation for Cyclic Combinational Circuits”, IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 14, No. 11.
Arvind Srinivasan et al., “Practical Analysis of Cyclic Combinational Circuits”, IEEE Custom Integrated Circuits Conference, 1996, pp. 381-384.
Thomas Robert Shiple et al., “Formal Analysis of Synchronous Circuits”, pp. 1-202.
Thomas R. Shiple et al., “Analysis of Combinational Cycles in Sequential Circuits”, IEEE International Symposium on Circuits and Systems, vol. 4, 1996, pp. 592-595.
Thomas R. Shiple et al., “Constructive Analysis of Cyclic Circuits”, Paris, Mar. 1996, pp. 1-6.
Robert de Simone, “Note: A Small Hardware Bus Arbiter Specification Leading Naturally to Correct Cyclec Description”, Mar. 1996, pp. 1-8.
Amar Bouali et al., “Verifying Synchronous Reactive Systems Programmed in ESTEREL”, pp. 1-4.
Stephen A. Edwards, “Making Cyclic Circuits Acyclic”, pp. 159-162.
R. K. Brayton et al., “Multilevel Log Synthesis”, Proceedings of the IEEE, vol. 78, No. 2, Feb. 1990, pp. 264-300.
Randal E. Bryant, “Boolean Analysis of MOS Circuits”, IEEE Trans. Computer-Aided Design, Feb. 1987, pp. 1-32.
R. Brayton et al., Logic Minimization Algorithms for VLSI Synthesis, Chapter 7, “Comparisons and Conclusions”, pp. 160-173, 1984.
J. Brzozowski et al., Asynchronous Circuits, Chapter 6, “Up-Bounded-Delay Race Models”, pp. 83-111, 1994.
J. Brzozowski et al., Asynchronous Circuits, Chapter 15, “Design of Asynchronous Circuits”, pp. 314-367, 1994.
Bruck Jehoshua
Riedel Marcus D.
California Institute of Technology
Lin Sun James
Townsend and Townsend and Crew
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