Synthesis aware placement: a novel approach that combines...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11040323

ABSTRACT:
A system and method improves the effectiveness of logic duplication optimizations by dynamically allocating the usage of logic duplicates. Duplicate atoms in the user design are identified. Atoms satisfying heuristics can also be duplicated and added to the user design. During placement, a duplicate-aware cost function is used to determine the location on the programmable device of atoms driven by a duplicate atom. The duplicate-aware cost function evaluates the suitability of a potential location of a driven atom with respect to a source atom and any duplicates of the source atom. Following placement of the atoms of the user design, a rewiring phase establishes a connection between each driven atom and one of the duplicated source atoms. The duplicate-aware cost function can be used to evaluate sets of duplicate source atoms to optimize the operating speed, power consumption, and/or routability of a user design.

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