Synchronous to asynchronous logic conversion

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

07739628

ABSTRACT:
Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.

REFERENCES:
patent: 7464361 (2008-12-01), Sandbote
patent: 7584449 (2009-09-01), Beerel et al.
patent: 7610567 (2009-10-01), Manohar
patent: 7614029 (2009-11-01), Manohar
patent: 2005/0160392 (2005-07-01), Sandbote
M. Amde et al., “Automating the Design of an Asynchronous DLX Microprocessor,” 2003 Design Automation Conference, pp. 502-507.
I. Blunno et al., “Handshake protocols for de-synchronization,” Proc. of the 10thInt'l Symposium on Asynchronous Circuits and Systems, 2004, 10 pages.
A. Branover et al., “Asynchronous Design by Conversion: Converting Synchronous Circuits into Asynchronous Ones,” Proc. of the Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 1-6.
E. Mercer et al., “Stochastic Cycle Period Analysis in Timed Circuits,” ISCAS 2000—IEEE Int'l Symposium on Circuits and Systems, pp. 172-175.
“International Application Serial No. PCT/US2009/033332, International Search Report and Written Opinion mailed Apr. 28, 2009”, 10 pgs.
Aimini, et al., “Globally Asynchronous lacally synchronous Wrapper Circuit based on clock gating”,Proceedings of the 2006emerging VLSI Technologies and architecture, (Mar. 2-3, 2006), 7 pages.
Cordetella, et al., “Desynchronisation :Synthesis of Asynchronous circuits from synchronous specifications”,IEEE Transaction on computer aided desing of integrated circuits and systems.vol. 25 No. 10, (Oct. 2006), pp. 1904-1921.
Oberg, et al., “Automatic synthesis of asynchronous circuits from synchronous RTL discriptions 2005”,23rd NORCHIP conference, (Nov. 1005), 21-22, 7 pages.
Smirnov, et al., “Synthesizing asynchronous micropipelines with desing compiler”,synopsys user groups ,boston, (2006), pp. 1-35.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Synchronous to asynchronous logic conversion does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous to asynchronous logic conversion, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous to asynchronous logic conversion will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4244111

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.